ARM ARM1176JZF-S Technical Reference Manual page 237

ARM DDI 0301H
ID012310
• Opcode_2 set to:
— 0, Primary Region Remap Register
— 1, Normal Memory Remap Register.
For example:
MRC p15, 0, <Rd>, c10, c2, 0
MCR p15, 0, <Rd>, c10, c2, 0
MRC p15, 0, <Rd>, c10, c2, 1
MCR p15, 0, <Rd>, c10, c2, 1
Memory remap occurs in two stages:
1. The processor uses the Primary Region Remap Register to remap the primary memory
type, Normal, Device, or Strongly Ordered, and the shareable attribute.
2. For memory regions that the Primary Region Remap Register defines as Normal memory,
the processor uses the Normal Memory Remap Register to remap the inner and outer
cacheable attributes.
The behavior of the memory region remap registers depends on the TEX remap bit, see c1,
Control Register on page 3-44. If the TEX remap bit is set, the entries in the memory region
remap registers remap each possible value of the TEX[0], C and B bits in the page tables. You
can therefore set your own definitions for these values. If the TEX remap bit is clear, the memory
region remap registers are not used and no memory remapping takes place. For more
information see Memory region attributes on page 6-14.
The memory region remap registers are expected to remain static during normal operation.
When you write to the memory region remap registers, you must invalidate the TLB and perform
an IMB operation before you can rely on the new written values. You must also stop the DMA
if it is running or queued.
Note
You cannot remap the NS bit. This is for security reasons.
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;Read Primary Region Remap Register
;Write Primary Region Remap Register
;Read Normal Memory Remap Register
;Write Normal Memory Remap Register
System Control Coprocessor
3-105