Figure 4-11 Load Word, Big-Endian; Figure 4-12 Store Word, Little-Endian - ARM ARM1176JZF-S Technical Reference Manual

4.3.12 Store word, little-endian
4.3.13 Store word, big-endian
ARM DDI 0301H
ID012310
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
The 32-bit general-purpose register is stored to four bytes in memory where bits [7:0] of the
ARM register are transferred to the least-significant addressed byte in memory, as Figure 4-12
shows.
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
The 32-bit general-purpose register is stored to four bytes in memory where bits [31:24] of the
ARM register are transferred to the most-significant addressed byte in memory, as Figure 4-13
on page 4-12 shows.
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Unaligned and Mixed-endian Data Access Support
Memory
7 0
Address
A[31:0]
B0 msbyte
+1 B1
+2 B2
+3 B3 lsbyte
Register
31 23 15 7
b3 b2 b1 b0
Register
31 23 15
B0 B1

Figure 4-11 Load word, big-endian

Memory
7
Address
A[31:0]
0
+1
+2
+3

Figure 4-12 Store word, little-endian

7 0
B2 B3
0
b0 lsbyte
b1
b2
b3 msbyte
4-11