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7.2.4
Cache miss handling
7.2.5
Cache disabled behavior
7.2.6
Unexpected hit behavior
ARM DDI 0301H
ID012310
Note
•
The cache operations executed in Secure state might affect all cache lines but cache
operations executed in Non-secure state only affect Non-secure lines.
•
You can restrict the functional size of each cache to 16KB, even when the physical cache
is larger. This enables the processor to run software that does not support ARMv6 page
coloring restrictions. You enable the this feature with the CZ bit, see c1, Auxiliary Control
Register on page 3-48.
For more information about ARMv6 page coloring see Restrictions on page table
mappings page coloring on page 6-41.
A cache miss results in the requests required to do the line fill being made to the level two
interface, with a Write-Back occurring if the line to be replaced contains dirty data.
The Write-Back data is transferred to the Write Buffer. This is arranged to handle this data as a
sequential burst. Because of the requirement for nonblocking caches, additional write
transactions can occur during the transfer of Write-Back data from the cache to the Write Buffer.
These transactions do not interfere with the burst nature of the Write-Back data. The Write
Buffer is responsible for handling the potential Read After Write (RAW) data hazards that might
exist from a Data Cache line Write-Back. The caches perform critical word-first cache refilling.
The internal bandwidth from the level two data read port to the Data Caches is eight bytes per
cycle, and supports streaming.
Cache miss handling when all ways are locked down
The ARM architecture describes the behavior of the cache as being Unpredictable when all ways
in the cache are locked down. However, for ARM1176JZF-S processors a cache miss is serviced
as if Way 0 is not locked.
If the cache is disabled, then the cache is not accessed for reads or for writes. This ensures that
maximum power savings can be achieved. It is therefore important that before the cache is
disabled, all of the entries are cleaned to ensure that the external memory has been updated. In
addition, if the cache is enabled with valid entries in it, then it is possible that the entries in the
cache contain old data. Therefore, the cache must be disabled with clean and invalid entries.
Cache maintenance operations can be performed even if the cache is disabled. The system can
disable the cache in Secure state when it is enabled in Non-secure state and enable the cache in
Secure state when it is disabled in Non-secure state.
An unexpected hit is where the cache reports a hit on a memory location that is marked as
Noncacheable or Shared. The unexpected hit behavior is that these hits are ignored and a level
two access occurs. The unexpected hit is ignored because the cache hit signal is qualified by the
cacheability.
For writes, an unexpected cache hit does not result in the cache being updated. Therefore, writes
appear to be Noncacheable accesses. For a data access, if it lies in the range of memory specified
by the Instruction TCM, then the access is made to that RAM rather than to level two memory.
This applies to both writes and reads.
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Level One Memory System
7-6
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