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ARM DDI 0301H
ID012310
This behavior describes most memory used in a system, and the term memory-like is used to
describe this sort of memory. In this section, writable normal memory and read-only normal
memory are not distinguished. Regions of memory with the Normal attribute can be Shared or
Non-Shared, on a per-page basis in the MMU. The marking of the same memory locations as
being Shared Normal and Non-Shared Normal in the MMU, for example by the use of
synonyms in a virtual to physical address mapping, results in Unpredictable behavior but this
does not break security. All explicit accesses to memory marked as Normal must correspond to
the ordering requirements of accesses that Ordering requirements for memory accesses on
page 6-23 describes. Accesses to Normal memory conform to the Weakly Ordered model of
memory ordering. A description of this model is in standard texts describing memory ordering
issues.
Shared Normal memory
The Shared Normal memory attribute is designed to describe normal memory that can be
accessed by multiple processors or other system masters. A region of memory marked as Shared
Normal is one where the effect of interposing a cache, or caches, on the memory system is
entirely transparent. Implementations can use a variety of mechanisms to support this, from not
caching accesses in shared regions to more complex hardware schemes for cache coherency for
those regions. The processor does not cache shareable locations at level one. In systems that
implement a TCM, the regions of memory covered by the TCM must not be marked as Shared.
The attributes for these regions are remapped to Inner and Outer Write-Back Non-Shared.
Writes to Shared Normal memory might not be atomic. That is, all observers might not see the
writes occurring at the same time. To preserve coherence where two writes are made to the same
location, the order of those writes must be seen to be the same by all observers. Reads to Shared
Normal memory that are aligned in memory to the size of the access are atomic.
Non-Shared Normal memory
The Non-Shared Normal memory attribute describes normal memory that can be accessed only
by a single processor. A region of memory marked as Non-Shared Normal does not have any
requirement to make the effect of a cache transparent.
Cacheable Write-Through, Cacheable Write-Back, and Noncacheable
In addition to marking a region of Normal memory as being Shared or Non-Shared, a region of
memory marked as Normal can also be marked on a per-page basis in an MMU as being one of:
•
Cacheable Write-Through
•
Cacheable Write-Back
•
Noncacheable.
This marking is independent of the marking of a region of memory as being Shared or
Non-Shared, and indicates the required handling of the data region for reasons other than those
to handle the requirements of shared data. As a result, a region of memory that is marked as
being Cacheable and Shared is not cached by the processor at level one. Marking the same
memory locations as having different Cacheable attributes, for example by the use of synonyms
in a virtual to physical address mapping, results in Unpredictable behavior but does not break
security.
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Memory Management Unit
6-21
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