Summary Of Differences; B.2 Summary Of Differences - ARM ARM1176JZF-S Technical Reference Manual

B.2

Summary of differences

B.2.1 TrustZone
ARM DDI 0301H
ID012310
The main differences between the ARM1136JF-S and ARM1176JZF-S processors are:
• TrustZone
• Power management on page B-4
• SmartCache on page B-5
• CPU ID on page B-5
• Block transfer operations on page B-5
• Tightly-Coupled Memories on page B-6
• Fault Address Register on page B-6
• Prefetch Unit on page B-7
• System control coprocessor operations on page B-7
• DMA on page B-9
• Debug on page B-10
• Level two interface on page B-10
• Memory BIST on page B-11.
The ARM1176JZF-S processor fully implements the TrustZone architecture for OS security
enhancements. This leads to numerous differences between ARM1136JF-S and
ARM1176JZF-S processors in the core and the Level 1 Memory System, see also Debug on
page B-10. The ARM1176JZF-S processor embodies, for TrustZone:
• operation in Secure or Non-secure states
• a new exception model
• a new mode, Secure Monitor mode
• a new instruction, SMC, to switch to Secure Monitor mode
• new CP15 registers to support the TrustZone architecture
• some CP15 registers that are:
— only accessible in Secure Privileged mode
— duplicated, banked, between Secure and Non-secure worlds
• a Level 1 Memory System that supports the Secure and Non-secure memory accesses
• a new NS attribute in the Level 1 page table descriptors to indicate if the targeted memory
is Secure or Non-secure.
• VA to PA operations
In addition:
• In the ARM1176JZF-S processor, in Non-secure state, the PLD instruction has no effect
on the memory system so it behaves like a NOP. In Secure state, this instruction behaves
as a cache preload instruction as implemented in ARM1136JF-S processor.
• The ARM1136JF-S CP15 c15 Cache Debug Control Register is the Cache Behavior
Override Register in the ARM1176JZF-S processor and is architectural with:
— Opcode_1=0
— Crn=9
— Crm=8
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Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
B-3