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11.5.1
Loads
ARM DDI 0301H
ID012310
Only the head instruction is involved in token exchange with the core pipeline, that does not
iterate instructions in this way, the tail instructions passing down the pipeline silently.
When an iterated load/store instruction is cancelled or flushed, all the tail instructions, bearing
the same tag, must be removed from the pipeline. Only the head instruction becomes a phantom
when cancelled. Any tail instruction can be left intact in the pipeline because it has no other
effect.
Because the cancel token is received in the coprocessor Ex1 stage, a cancelled iterated
instruction always consists of a head instruction in Ex1 and a single tail instruction in the issue
stage.
Load data emerge from the WBls stage of the core LSU and are received by the coprocessor Ex6
stage. Each item in a vectored load is picked up by one instance of the iterated load instruction.
The pipeline timing means that a load instruction is always ready, or arrived a short time ago, in
Ex6 to pick up each data item. If a load instruction has arrived in Ex6, but the load information
has not yet appeared, the load instruction must stall in Ex6, stalling the rest of the coprocessor
pipeline.
The following signals are driven by the core to pass load data across to the coprocessor:
ACPLDVALID
This signal, when set, indicates that the associated data are valid.
ACPLDDATA[63:0]
This is the information passed from the core to the coprocessor.
Load buffers
To achieve correct alignment of the load data with the load instruction in the coprocessor Ex6
stage, the data must be double buffered when they arrive at the coprocessor. Figure 11-10 on
page 11-17 shows an example.
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Figure 11-9 Instruction iteration for loads
Coprocessor Interface
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