Figure 14-9 Scan Chain 4 Bit Order - ARM ARM1176JZF-S Technical Reference Manual

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DBGTDI
ARM DDI 0301H
ID012310
Scan chain 4, instruction transfer register (ITR)
Purpose
Debug
Length
1 + 32 = 33 bits
Description This scan chain accesses the Instruction Transfer Register (ITR), used to send
instructions to the core through the Prefetch Unit (PU). It consists of 32 bits of
information, plus an additional bit to indicate the completion of the instruction
sent to the core, InstCompl. The InstCompl bit is read-only.
While in Debug state, an instruction loaded into the ITR can be issued to the core
by making the DBGTAPSM go through the Run-Test/Idle state. The InstCompl
flag is cleared when the instruction is issued to the core and set when the
instruction completes.
For an instruction to be issued when going through Run-Test/Idle state, you must
ensure the following conditions are met:
The processor must be in Debug state.
The DSCR[13] execute ARM instruction enable bit must be set. For details
of the DSCR see CP14 c1, Debug Status and Control Register (DSCR) on
page 13-7.
Scan chain 4 or 5 must be selected.
INTEST or EXTEST must be selected.
Ready flag must be captured set. That is, the last time the DBGTAPSM
went through Capture-DR the InstCompl flag must have been set.
The DSCR[6] sticky precise Data Abort flag must be clear. This flag is set
on precise Data Aborts.
For an instruction to be loaded into the ITR when going through Update-DR, you
must ensure the following conditions are met:
The processor can be in any state.
The value of DSCR[13] execute ARM instruction enable bit does not
matter.
Scan chain 4 must be selected.
EXTEST must be selected.
Ready flag must be captured set. That is, the last time the DBGTAPSM
went through Capture-DR the InstCompl flag must have been set.
The value of DSCR[6] sticky precise Data Abort flag does not matter.
Order
Figure 14-9 shows the order of bits in scan chain 4.
InstCompl
32 31
Ready
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Data[31:0]
ITR[31:0]

Figure 14-9 Scan chain 4 bit order

Debug Test Access Port
0
DBGTDO
14-13

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