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2.10.5
The E bit
2.10.6
The A bit
2.10.7
The control bits
ARM DDI 0301H
ID012310
ARM and Thumb instructions are provided to set and clear the E-bit. The E bit controls
load/store endianness. For details of where the E bit is used see Chapter 4 Unaligned and
Mixed-endian Data Access Support.
Architecture versions prior to ARMv6 specify this bit as SBZ. This ensures no endianness
reversal on loads or stores.
The A bit is set automatically. It is used to disable imprecise Data Aborts. It might be not
writable in the Non-secure world if the AW bit in the SCR register is reset. For details of how
to use the A bit see Imprecise Data Abort mask in the CPSR/SPSR on page 2-47.
The bottom eight bits of a PSR are known collectively as the control bits. They are the:
•
Interrupt disable bits
•
T bit
•
Mode bits on page 2-28.
The control bits change when an exception occurs. When the processor is operating in a
privileged mode, software can manipulate these bits.
Interrupt disable bits
The I and F bits are the interrupt disable bits:
•
When the I bit is set, IRQ interrupts are disabled.
•
When the F bit is set, FIQ interrupts are disabled. FIQ can be non-maskable in the
Non-secure world if the FW bit in SCR register is reset
Note
You can change the SPSR F bit in the Non-secure world but this does not update the CPSR if
the SCR bit 4 (FW) does not permit it.
T bit
The T bit reflects the operating state:
•
when the T bit is set, the processor is executing in Thumb state
•
when the T bit is clear, the processor is executing in ARM state, or Jazelle state depending
on the J bit.
Note
Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If an MSR
instruction does try to modify this bit the result is architecturally Unpredictable. In the
ARM1176JZF-S processor this bit is not affected.
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Programmer's Model
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