Figure 6-9 Armv6 Section, Supersection, And Page Translation - ARM ARM1176JZF-S Technical Reference Manual

6.11.3 Restrictions on page table mappings page coloring
ARM DDI 0301H
ID012310
First level
page table
Translation
table base
Invalid
Indexed by
VA[31:20]
(bit 18 = 0) 10
(bit 18 = 1) 10
The processor uses virtually indexed, physically addressed caches. To prevent alias problems
where cache sizes greater than 16KB have been implemented, you must restrict the mapping of
pages that remap virtual address bits [13:12].
• for the Instruction Cache, the Isize P bit, bit[11], of the Cache Type Register CP15 c0,
indicates if this is necessary
• for the Data Cache, the Dsize P bit, bit[23], of the Cache Type Register CP15 c0, indicates
if this is necessary.
See c0, Cache Type Register on page 3-21 for more information.
This restriction, referred to as page coloring, enables the virtual address bits[13:12] to be used
to index into the cache without requiring hardware support to avoid alias problems.
For pages marked as Non-Shared, if bit 11 or bit 23 of the Cache Type Register is set, the
restriction applies to pages that remap virtual address bits [13:12] and might cause aliasing
problems when 4KB pages are used. To prevent this you must ensure the following restrictions
are applied:
1. If multiple virtual addresses are mapped onto the same physical address then for all
mappings of bits [13:12] the virtual addresses must be equal and the same as bits [13:12]
of the physical address. The same physical address can be mapped by TLB entries of
different page sizes, including page sizes over 4KB. Imposing this requirement on the
virtual address is called page coloring.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
00
Coarse page
Base address
31
from L1D[31:10]
Indexed by
01
VA[19:12]
1MB section
Base address
from L1D[31:20]
Indexed by
VA[19:0]
supersection
Base address
from L1D[31:24]
Indexed by
VA[23:0]

Figure 6-9 ARMv6 section, supersection, and page translation

Memory Management Unit
Base address
from L2D[31:16]
table
Indexed by
0
VA[15:0]
Invalid 00
01
Base address
1
from L2D[31:12]
XN
Indexed by
VA[11:0]
16MB
64KB large page
31 0
4KB extended
small page
31 0
6-41