Table 21-2 Single-Precision Source Register Clearing - ARM ARM1176JZF-S Technical Reference Manual

21.6.3 Single-precision source register clearing
ARM DDI 0301H
ID012310
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the Execute 1 stage of the iteration. In RunFast mode, the source registers for only iterations 5,
6, 7, and 8 are locked, and the source scoreboard begins clearing them in the second Execute 1
cycle of the instruction. Table 21-2 summarizes source register clearing in single-precision
operations.
Execute 1 cycle
1
2
3
4
5
6
7
8
For the following single-precision short vector instruction, the LEN field contains b100,
selecting a vector length of five iterations:
FADDS S8, S16, S24
The FADDS instruction performs the following operations:
FADDS S8, S16, S24
FADDS S9, S17, S25
FADDS S10, S18, S26
FADDS S11, S19, S27
FADDS S12, S20, S28
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the Execute 1 cycle of the iteration.
In RunFast mode, the source scoreboard locks only the fifth iteration source registers, S20 and
S28. It clears S20 and S28 in the second Execute 1 cycle of the instruction.
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Table 21-2 Single-precision source register clearing

Source registers cleared in Execute 1 stage of each iteration
Full-compliance mode
Iteration 1 registers
Iteration 2 registers
Iteration 3 registers
Iteration 4 registers
Iteration 5 registers
Iteration 6 registers
Iteration 7 registers
Iteration 8 registers
VFP Instruction Execution
RunFast mode
-
Iteration 5 registers
Iteration 6 registers
Iteration 7 registers
Iteration 8 registers
-
-
-
21-9