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6.2.2
Main TLB
6.2.3
TLB control operations
6.2.4
Page-based attributes
ARM DDI 0301H
ID012310
The main TLB is the second layer in the TLB structure that catches the cache misses from the
MicroTLBs. It provides a centralized source for translation entries.
Misses from the instruction and data MicroTLBs are handled by a unified main TLB, that is
accessed only on MicroTLB misses. Accesses to the main TLB take a variable number of cycles,
according to competing requests between each of the MicroTLBs and other
implementation-dependent factors. Entries in the lockable region of the main TLB are lockable
at the granularity of a single entry, as c10, TLB Lockdown Register on page 3-100 describes.
Main TLB implementation
The main TLB is implemented as a combination of two elements:
•
A fully-associative array of eight elements, that is lockable.
You can restrict this region to store Secure entries only, that is entries with NSTID=0,
when the TL bit is clear in the NSAC register, see c1, Non-Secure Access Control Register
on page 3-55
Note
—
If you clear the TL bit, after creating some NS entries in the Lockdown region, this
does not invalidate these entries. The TL bit prevents the creation of new NS entries
in the Lockdown region.
—
The TL bit has no influence on the Read/Write Lockdown entry operations, VA PA
or Attributes, in the system control coprocessor, see c15, TLB lockdown access
registers on page 3-149. When the TL bit is set, the processor can write an NS entry
in the Lockdown region with the Write Lockdown operation of the system control
coprocessor.
•
A low-associativity Tag RAM and DataRAM structure similar to that used in the Cache.
The implementation of the low-associativity region is a 64-entry 2-way associative structure.
Depending on the RAMs available, you can implement this as either:
•
four 32-bit wide RAMs
•
two 64-bit wide RAMs
•
a single 128-bit wide RAM.
Main TLB misses
Main TLB misses are handled in hardware by the two level page table walk mechanism, as used
on previous ARM processors. See c8, TLB Operations Register on page 3-86.
Note
Automatic page table walks might be disabled by PD0 and PD1 bits in the TTB Control register.
c8, TLB Operations Register on page 3-86 and c10, TLB Lockdown Register on page 3-100
describe the TLB control operations.
Memory access control on page 6-11 describe the page-based attributes for access protection.
Memory region attributes on page 6-14 and Memory attributes and types on page 6-20 describe
the memory types and page-based cache control attributes. The processor interprets the Shared
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