Table 3-149 Tlb Lockdown Va Register Bit Functions; Table 3-150 Tlb Lockdown Pa Register Bit Functions; Figure 3-78 Tlb Lockdown Pa Register Format - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[31:12] VA
[11:10] -
[9] G
[8] -
[7:0] ASID
Bits Field name
[31:12] PA
[11:10] -
[9] NSA
[8] NSTID
[7:6] Size
[5:4] -
ARM DDI 0301H
ID012310
Table 3-149 lists how the bit values correspond with the TLB Lockdown VA Register functions.
Function
Holds the VA of this page table entry.
UNP/SBZ.
Defines if this page table entry is global, applies to all ASIDs, or application-specific, ASID
must match on lookups:
0 = Application-specific entry
1 = Global entry.
UNP/SBZ.
Holds the ASID for application-specific page table entries. For global entries, this field Should
Be Zero.
Figure 3-78 shows the arrangement of bits in the TLB Lockdown PA Register.
31
Table 3-150 lists how the bit values correspond with the TLB Lockdown PA Register functions.
Function
Holds the PA of this page table entry.
UNP/SBZ.
Defines whether memory accesses in the memory region that this page table entry describes are
Secure or Non-secure accesses. This matches the Secure or Non-secure state of the memory
being accessed. If the NSTID bit is set, the NSA bit is also set regardless of the written value.
This ensures that Non-secure page table entries can only access Non-secure memory, but
Secure page table entries can access Secure or Non-secure memory:
0 = Memory accesses are Secure
1 = Memory accesses are Non-secure.
Defines page table entry as Secure or Non-secure:
0 = Entry is Secure
1 = Entry is Non-secure.
Defines the size of the memory region that this page table entry describes:
b00 = 16MB supersection
b01 = 4KB page
b10 = 64KB page
b11 = 1M section.
UNP/SBZ.
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Table 3-149 TLB Lockdown VA Register bit functions

PA

Figure 3-78 TLB Lockdown PA Register format

Table 3-150 TLB Lockdown PA Register bit functions

System Control Coprocessor
12 11 10 9 8 7 6 5 4 3 2 1 0
N
SBZ S Size SBZ
A
NSTID
A
P AP V
X
3-150