Table 2-6 Ge[3:0] Settings - ARM ARM1176JZF-S Technical Reference Manual

2.10.4 The GE[3:0] bits
Instruction
Signed
SADD16
SSUB16
SADDSUBX
SSUBADDX
SADD8
SSUB8
Unsigned
UADD16
USUB16
UADDSUBX
USUBADDX
UADD8
USUB8
ARM DDI 0301H
ID012310
• The placement of the J bit avoids the status or extension bytes in code running on
ARMv5TE or earlier processors. This ensures that OS code written using the deprecated
CPSR, SPSR, CPSR_all, or SPSR_all syntax for the destination of an MSR instruction
continues to work.
Some of the SIMD instructions set GE[3:0] as greater-than-or-equal bits for individual
halfwords or bytes of the result. Table 2-6 lists these.
GE[3]
A op B >= C
[31:16] + [31:16] ≥ 0
[31:16] - [31:16] ≥ 0
[31:16] + [15:0] ≥ 0
[31:16] - [15:0] ≥ 0
[31:24] + [31:24] ≥ 0
[31:24] - [31:24] ≥ 0
[31:16] + [31:16] ≥ 2
16
[31:16] - [31:16] ≥ 0
[31:16] + [15:0] ≥ 2
16
[31:16] - [15:0] ≥ 0
[31:24] + [31:24] ≥ 2
8
[31:24] - [31:24] ≥ 0
Note
GE bit is 1 if A op B ≥ C, otherwise 0.
The SEL instruction uses GE[3:0] to select the source register that supplies each byte of its
result.
Note
• For unsigned operations, the GE bits are determined by the usual ARM rules for carries
out of unsigned additions and subtractions, and so are carry-out bits.
• For signed operations, the rules for setting the GE bits are chosen so that they have the
same sort of greater than or equal functionality as for unsigned operations.
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GE[2] GE[1]
A op B >= C A op B >= C
[31:16] + [31:16] ≥ 0 [15:0] + [15:0] ≥ 0
[31:16] - [31:16] ≥ 0 [15:0] - [15:0] ≥ 0
[31:16] + [15:0] ≥ 0 [15:0] - [31:16] ≥ 0
[31:16] - [15:0] ≥ 0 [15:0] + [31:16] ≥ 0
[23:16] + [23:16] ≥ 0 [15:8] + [15:8] ≥ 0
[23:16] - [23:16] ≥ 0 [15:8] - [15:8] ≥ 0
[31:16] + [31:16] ≥ 2 [15:0] + [15:0] ≥ 2
16
[31:16] - [31:16] ≥ 0 [15:0] - [15:0] ≥ 0
[15:0] - [31:16] ≥ 0
[31:16] + [15:0] ≥ 2
16
[31:16] - [15:0] ≥ 0
[15:0] + [31:16] ≥ 2
[23:16] + [23:16] ≥ 2 [15:8] + [15:8] ≥ 2
8
[23:16] - [23:16] ≥ 0 [15:8] - [15:8] ≥ 0
Programmer's Model

Table 2-6 GE[3:0] settings

GE[0]
A op B >= C
[15:0] + [15:0] ≥ 0
[15:0] - [15:0] ≥ 0
[15:0] - [31:16] ≥ 0
[15:0] + [31:16] ≥ 0
[7:0] + [7:0] ≥ 0
[7:0] - [7:0] ≥ 0
[15:0] + [15:0] ≥ 2
16 16
[15:0] - [15:0] ≥ 0
[15:0] - [31:16] ≥ 0
[15:0] + [31:16] ≥2
16 16
[7:0] + [7:0] ≥ 2
8 8
[7:0] - [7:0] ≥ 0
2-26