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3.2.6
c0, CPUID registers
Bits
[31:28]
[27:24]
[23:20]
ARM DDI 0301H
ID012310
For example:
MRC p15,0,<Rd>,c0,c0,3
The section describes the CPUIID registers:
•
c0, Processor Feature Register 0
•
c0, Processor Feature Register 1 on page 3-27
•
c0, Debug Feature Register 0 on page 3-29
•
c0, Auxiliary Feature Register 0 on page 3-30
•
c0, Memory Model Feature Register 0 on page 3-31
•
c0, Memory Model Feature Register 1 on page 3-32
•
c0, Memory Model Feature Register 2 on page 3-33
•
c0, Memory Model Feature Register 3 on page 3-35
•
c0, Instruction Set Attributes Register 0 on page 3-36
•
c0, Instruction Set Attributes Register 1 on page 3-37
•
c0, Instruction Set Attributes Register 2 on page 3-39
•
c0, Instruction Set Attributes Register 3 on page 3-40
•
c0, Instruction Set Attributes Register 4 on page 3-42
•
c0, Instruction Set Attributes Register 5 on page 3-43.
Note
The CPUID registers are sometimes described as the Core Feature ID registers.
c0, Processor Feature Register 0
The purpose of the Processor Feature Register 0 is to provide information about the execution
state support and programmer's model for the processor.
Processor Feature Register 0 is:
•
in CP15 c0
•
a 32-bit read-only register common to the Secure and Non-secure worlds
•
accessible in privileged modes only.
Table 3-12 lists how the bit values correspond with the Processor Feature Register 0 functions.
Figure 3-14 shows the bit arrangement for Processor Feature Register 0.
31
28 27
24 23
Reserved
Reserved
Field name
Function
-
Reserved. RAZ.
-
Reserved. RAZ.
-
Reserved. RAZ.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
; returns TLB details
20 19
16 15
Reserved
Reserved
State3
Figure 3-14 Processor Feature Register 0 format
Table 3-12 Processor Feature Register 0 bit functions
System Control Coprocessor
12 11
8 7
4 3
State2
State1
0
State0
3-26
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