About The Processor Vic Port; Table 12-1 Vic Port Signals; Figure 12-1 Connection Of A Vic To The Processor - ARM ARM1176JZF-S Technical Reference Manual

12.2

About the processor VIC port

Signal name
nFIQ
nIRQ
INTSYNCEN
IRQADDRVSYNCEN
IRQACK
IRQADDRV
IRQADDR[31:2]
ARM DDI 0301H
ID012310
Figure 12-1 shows the VIC port and the Peripheral Interface connecting a PL192 VIC and the
processor.
Processor
INTSYNCEN
IRQADDRVSYNCEN
nFIQ
nIRQ
IRQACK
IRQADDRV
IRQADDR[31:2]
Note
Do not be confused by the naming of the IRQADDRVSYNCEN and nVICSYNCEN signals.
Although one is active HIGH and the other is active LOW they are connected to a common
external synchronization disable signal. See the signal descriptions in Table 12-1 for more
information.
The VIC port enables the processor to read the vector address as part of the IRQ interrupt entry.
That is, the processor takes a vector address from this interface instead of using the legacy
or .The VIC port does not support the reading of FIQ vector addresses.
0x00000018 0xFFFF0018
The interrupt interface is designed to handle interrupts asserted by a controller that is clocked
either synchronously or asynchronously to the processor clock. This capability ensures that the
controller can be used in systems that have either a synchronous or asynchronous interface
between the core clock and the AXI clock.
The VIC port consists of the signals that Table 12-1 lists.
Direction Description
Input Active LOW fast interrupt request signal
Input Active LOW normal interrupt request signal
If this signal is asserted HIGH, the internal nFIQ and nIRQ synchronizers are
Input
bypassed and the interface is synchronous
If this signal is asserted HIGH, the internal IRQADDRV synchronizer is
Input
bypassed and the interface is synchronous
Output Active HIGH IRQ acknowledge
Input Active HIGH valid signal for the IRQ interrupt vector address below
IRQ interrupt vector address. IRQADDR[31:2] holds the address of the first
Input
ARM state instruction in the IRQ handler
IRQACK is driven by the processor to indicate to an external VIC that the processor wants to
read the IRQADDR input.
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VIC
0
nVICSYNCEN
nVICFIQ
nVICIRQ
VICIRQACK
VICIRQADDRV
VICVECTADDROUT[31:2]

Figure 12-1 Connection of a VIC to the processor

Vectored Interrupt Controller Port
VICINTSOURCE[(N-1):0]
nVICFIQIN
nVICIRQIN
VICVECTADDRIN[31:0]

Table 12-1 VIC port signals

12-3