ARM ARM1176JZF-S Technical Reference Manual page 562

14.8.10 Reading the PC
14.8.11 Writing the PC
14.8.12 General notes about reading and writing memory
14.8.13 Reading memory as words
ARM DDI 0301H
ID012310
Here R0 is used as a temporary register:
1. Move the contents of the PC to R0:
ITRSEL
INST MOV R0,PC
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
2. Read the contents of R0 using the standard sequence that Reading a current mode ARM
register in the range R0-R14 on page 14-34 describes.
Here R0 is used as a temporary register:
1. Load R0 with the address to resume using the standard sequence that Writing a current
mode ARM register in the range R0-R14 on page 14-34 describes. Now scan chain 5 and
EXTEST are selected.
2. Move the contents of R0 to the PC:
ITRSEL
INST MOV PC,R0
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
The word-based read and write sequences are substantially more efficient than the halfword and
byte sequences. This is because the ARM LDC and STC instructions always perform word
accesses, and this can be used for efficient access to word width memory. Halfword and byte
accesses must be done with a combination of loads or stores, and coprocessor register transfers.
This is much less efficient. When writing data, the Instruction Cache might become incoherent.
In those cases, the appropriate part of the Instruction Cache must be invalidated. In particular,
the Instruction Cache must be invalidated before setting a software breakpoint or downloading
code.
This sequence is optimized for a long sequential read. This sequence assumes that R0 has been
set to the address to load data from prior to running this sequence. R0 is post-incremented so
that it can be used by successive reads of memory.
1. Load and issue the LDC instruction:
SCAN_N 5
ITRSEL
INST LDC p14,c5,[R0],#4
RTI
2. The DTR is selected to read the data:
INTEST
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; select the ITR and EXTEST
; wait until the instruction ends
; select the ITR and EXTEST
; wait until the instruction ends
; select DTR
; select the ITR and EXTEST
; load the content of the position of
; memory pointed by R0 into wDTR and
; increment R0 by 4
; select the DTR and INTEST
Debug Test Access Port
14-36