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20.1
About the programmer's model
ARM DDI 0301H
ID012310
This section introduces the VFP11 implementation of the VFPv2 floating-point architecture.
Note
The ARM Architecture Reference Manual describes the VFPv1 architecture.
The VFP11 coprocessor implements all the instructions and modes of the VFPv2 architecture.
The VFPv2 architecture adds the following features and enhancements to the VFPv1
architecture:
•
The ARM v5TE instruction set. This includes the MRRC and MCRR instructions to
transfer 64-bit data between the ARM11 processor and the VFP11 coprocessor. These
instructions enable the transfer of a double-precision register or two consecutively
numbered single-precision registers to or from a pair of ARM11 registers. See Loading
operands from ARM11 registers on page 19-6 for syntax and usage of VFP MRRC and
MCRR instructions.
•
Default NaN mode. In default NaN mode, any operation involving one or more NaN
operands produces the default NaN as a result, rather than returning the NaN or one of the
NaNs involved in the operation. This mode is compatible with the IEEE 754 standard but
not with current handling of NaNs by industry.
•
Addition of the input subnormal flag, IDC (FPSCR[7]). IDC is set whenever the VFP11
coprocessor is in flush-to-zero mode and a subnormal input operand is replaced by a
positive zero. It remains set until cleared by writing to the FPSCR register. A new Input
Subnormal exception enable bit, IDE (FPSCR[15]), is also added. When IDE is set, the
VFP11 coprocessor traps to the Undefined trap handler for an instruction that has a
subnormal input operand.
•
New functionality of the underflow flag, UFC (FPSCR[3]), in flush-to-zero mode. In
flush-to-zero mode, UFC is set whenever a result is lower than the threshold for normal
numbers before rounding, and the result is flushed to zero. UFC remains set until cleared
by writing to the FPSCR register. Setting the Underflow exception enable bit, UFE
(FPSCR[11]), does not cause a trap in flush-to-zero mode.
•
New functionality of the inexact flag, IXC (FPSCR[4]), in flush-to-zero mode. In VFPv1,
IXC is set when an input or result is flushed to zero. In VFPv2 architecture, the IDC and
UFC flags provide this information. See Inexact exception on page 22-18 for more
information.
•
Addition of RunFast mode. See RunFast mode on page 18-12 for details of RunFast mode
operation.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
VFP Programmer's Model
20-2
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