13.16 External Signals - ARM ARM1176JZF-S Technical Reference Manual

13.16 External signals

ARM DDI 0301H
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The following external signals are used by debug:
DBGACK Debug acknowledge signal. The processor asserts this output signal to
indicate the system has entered Debug state. See Debug state on
page 13-37 for a definition of the Debug state.
DBGEN Debug enable signal. When this signal is LOW, DSCR[15:14] is read as 0
and the processor cannot enter Debug state.
EDBGRQ External debug request signal. As External debug request signal on
page 13-32 describes, this input signal forces the core into Debug state if
the Debug logic is enabled by DBGEN and debug is permitted.
DBGNOPWRDWN
Powerdown disable signal generated from DSCR[9]. When this signal is
HIGH, the system power controller is forced into Emulate mode. This is
to avoid losing CP14 Debug state that can only be written through the
DBGTAP. Therefore, DSCR[9] must only be set if Halting debug-mode
debugging is necessary.
SPIDEN Secure Privileged Invasive Debug Enable input signal, as Secure Monitor
mode and debug on page 13-4 describes.
SPNIDEN Secure Privileged Non-invasive Debug Enable input signal, as Secure
Monitor mode and debug on page 13-4 describes.
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