ARM ARM1176JZF-S Technical Reference Manual page 755

Reserved
Rounding mode
RunFast mode
Saved Program Status Register (SPSR)
SBO
SBZ
SBZP
Scalar operation
Scan chain
SCREG
Set
Set-associative cache
ARM DDI 0301H
ID012310
A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These
fields are reserved for use in future extensions of the architecture or are
implementation-specific. All reserved bits not used by the implementation must be written as 0
and read as 0.
The IEEE 754 standard requires all calculations to be performed as if to an infinite precision.
For example, a multiply of two single-precision values must accurately calculate the significand
to twice the number of bits of the significand. To represent this value in the destination precision,
rounding of the significand is often required. The IEEE 754 standard specifies four rounding
modes.
In round-to-nearest mode, the result is rounded at the halfway point, with the tie case rounding
up if it would clear the least significant bit of the significand, making it even.
Round-towards-zero mode chops any bits to the right of the significand, always rounding down,
and is used by the C, C++, and Java languages in integer conversions.
Round-towards-plus-infinity mode and round-towards-minus-infinity mode are used in interval
arithmetic.
In RunFast mode, hardware handles exceptional conditions and special operands. RunFast mode
is enabled by enabling default NaN and flush-to-zero modes and disabling all exceptions. In
RunFast mode, the VFP11 coprocessor does not bounce to the support code for any legal
operation or any operand, but supplies a result to the destination. For all inexact and overflow
results and all invalid operations that result from operations not involving NaNs, the result is as
specified by the IEEE 754 standard. For operations involving NaNs, the result is the default
NaN.
The register that holds the CPSR of the task immediately before the exception occurred that
caused the switch to the current mode.
See Should Be One.
See Should Be Zero.
See Should Be Zero or Preserved.
A VFP coprocessor operation involving a single source register and a single destination register.
See also Vector operation.
A scan chain is made up of serially-connected devices that implement boundary scan technology
using a standard JTAG TAP interface. Each device contains at least one TAP controller
containing shift registers that form the chain connected between TDI and TDO, through which
test data is shifted. Processors can contain several shift registers to enable you to access selected
parts of the device.
The currently selected scan chain number in an ARM TAP controller.
See Cache set.
In a set-associative cache, lines can only be placed in the cache in locations that correspond to
the modulo division of the memory address by the number of sets. If there are n ways in a cache,
the cache is termed n-way set-associative. The set-associativity can be any number greater than
or equal to 1 and is not restricted to being a power of two.
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