ARM ARM1176JZF-S Technical Reference Manual page 618

18.4.2 DS pipeline
ARM DDI 0301H
ID012310
FCMPE Compare, NaN exceptions.
FCMPZ Compare with zero.
FCMPEZ Compare with zero, NaN exceptions.
FCVTSD Convert from double-precision to single-precision.
FCVTDS Convert from single-precision to double-precision.
FCPY Copy register.
See Execution timing on page 21-22 for cycle counts. The FMAC family of instructions. FMAC,
FNMAC, FMSC, and FNMSC, perform a chained multiply and accumulate operation. The
product is computed, rounded according to the specified rounding mode and destination
precision, and checked for exceptions before the accumulate operation is performed. The
accumulate operation is also rounded according to the specified rounding mode and destination
precision and checked for exceptions. The final result is identical to the equivalent sequence of
operations executed in sequence. Exception processing and status reporting also reflect the
independence of the components of the chained operations.
As an example, the FMAC instruction performs a chained multiply and add operation with the
following sequence of operations:
1. The product of the operands in the Fn and Fm registers is computed.
2. The product is rounded according to the current rounding mode and destination precision
and checked for exceptions.
3. The result is summed with the operand in the Fd register.
4. The sum is rounded according to the current rounding mode and destination precision and
checked for exceptions. If no exception conditions that require support code are present,
the result is written to the Fd register.
For example, the following two operations return the same result:
FMACS S0, S1, S2
FMULS TEMP, S1, S2
FADDS S0, S0, TEMP
Figure 18-2 on page 18-8 shows the structure of the DS pipeline.
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Introduction to the VFP coprocessor
18-7