ARM ARM1176JZF-S Technical Reference Manual page 745

Block address
Bounce
Boundary scan chain
Branch folding
Branch phantom
Branch prediction
Breakpoint
Burst
Byte
ARM DDI 0301H
ID012310
- a byte at a halfword-aligned address is the most significant byte within the halfword at that
address.
See also Little-endian memory.
An address that comprises a tag, an index, and a word field. The tag bits identify the way that
contains the matching cache entry for a cache hit. The index bits identify the set being
addressed. The word field contains the word address that can be used to identify specific words,
halfwords, or bytes within the cache entry.
See also Cache terminology diagram on the last page of this glossary.
The VFP coprocessor bounces an instruction when it fails to signal the acceptance of a valid
VFP instruction to the ARM processor. This action initiates Undefined instruction processing
by the ARM processor. The VFP support code is called to complete the instruction that was
found to be exceptional or unsupported by the VFP coprocessor.
See also Trigger instruction, Potentially exceptional instruction, and Exceptional state.
A boundary scan chain is made up of serially-connected devices that implement boundary scan
technology using a standard JTAG TAP interface. Each device contains at least one TAP
controller containing shift registers that form the chain connected between TDI and TDO,
through which test data is shifted. Processors can contain several shift registers to enable you to
access selected parts of the device.
Branch folding is a technique where, on the prediction of most branches, the branch instruction
is completely removed from the instruction stream presented to the execution pipeline. Branch
folding can significantly improve the performance of branches, taking the CPI for branches
lower than one.
The condition codes of a predicted taken branch.
The process of predicting if conditional branches are to be taken or not in pipelined processors.
Successfully predicting if branches are to be taken enables the processor to prefetch the
instructions following a branch before the condition is fully resolved. Branch prediction can be
done in software or by using custom hardware. Branch prediction techniques are categorized as
static, in which the prediction decision is decided before run time, and dynamic, in which the
prediction decision can change during program execution.
A breakpoint is a mechanism provided by debuggers to identify an instruction at which program
execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of
register contents, memory locations, variable values at fixed points in the program execution to
test that the program is operating correctly. Breakpoints are removed after the program is
successfully tested.
See also Watchpoint.
A group of transfers to consecutive addresses. Because the addresses are consecutive, there is
no requirement to supply an address for any of the transfers after the first one. This increases the
speed at which the group of transfers can occur. Bursts over AXI buses are controlled using the
AxBURST signals to specify if transfers are single, four-beat, eight-beat, or 16-beat bursts, and
to specify how the addresses are incremented.
See also Beat.
An 8-bit data item.
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Glossary
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