Registers; Figure - ARM ARM1176JZF-S Technical Reference Manual

2.9

Registers

2.9.1 The ARM state core register set
ARM DDI 0301H
ID012310
The processor has a total of 40 registers:
• 33 general-purpose 32-bit registers
• seven 32-bit status registers.
These registers are not all accessible at the same time. The processor state and operating mode
determine the registers that are available to the programmer.
In ARM state, 16 general registers and one or two status registers are accessible at any time. In
privileged modes, mode-specific banked registers become available. Figure 2-6 on page 2-20
shows the registers that are available in each mode.
The ARM state core register set contains 16 directly-accessible registers, R0-R15. Another
register, the Current Program Status Register (CPSR), contains condition code flags, status bits,
and current mode bits. Registers R0-R12 are general-purpose registers used to hold either data
or address values. Registers R13, R14, R15, and the Saved Program Status Register (SPSR)
have the following special functions:
Stack Pointer Register R13 is used as the Stack Pointer (SP).
R13 is banked for the exception modes. This means that an exception
handler can use a different stack to the one in use when the exception
occurred.
In many instructions, you can use R13 as a general-purpose register, but
the architecture deprecates this use of R13 in most instructions. For more
information see the ARM Architecture Reference Manual.
Link Register Register R14 is used as the subroutine Link Register (LR).
Register R14 receives the return address when a Branch with Link (BL or
BLX) instruction is executed.
You can treat R14 as a general-purpose register at all other times. The
corresponding banked registers R14_mon, R14_svc, R14_irq, R14_fiq,
R14_abt, and R14_und are similarly used to hold the return values when
interrupts and exceptions arise, or when BL or BLX instructions are
executed within interrupt or exception routines.
Program Counter Register R15 holds the PC:
•
•
•
Saved Program Status Register
In privileged modes, another register, the SPSR, is accessible. This
contains the condition code flags, status bits, and current mode bits saved
as a result of the exception that caused entry to the current mode.
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in ARM state this is word-aligned
in Thumb state this is halfword-aligned
in Jazelle state this is byte-aligned.
Programmer's Model
2-18