ARM ARM1176JZF-S Technical Reference Manual page 118

2.12.10 Aborts
ARM DDI 0301H
ID012310
• The second alternative is to use IRQs for all but the highest priority interrupt, so that there
is only one level of FIQ interrupt. This achieves very fast FIQ latency, 5-8 cycles, but at a
cost to all the lower-priority interrupts that every exception entry sequence now disables
them. You then have the following possibilities:
— None of the exception handlers in the architectural completion layer re-enable
IRQs. In this case, all IRQs suffer from additional possible interrupt latency caused
by those handlers, and so effectively are in the non real-time layer. In other words,
this results in there only being one priority for interrupts in the real-time layer.
— All of the exception handlers in the architectural completion layer re-enable IRQs
to permit IRQs to have real-time behavior. The problem in this case is that all IRQs
can then occur during the processing of an exception in the architectural completion
layer, and so they are all effectively in the real-time layer. In other words, this
effectively means that there are no interrupts in the non real-time layer.
— All of the exception handlers in the architectural completion layer re-enable IRQs,
but they also use additional VIC facilities to place a lower limit on the priority of
IRQs that is taken. This permits IRQs at that priority or higher to be treated as being
in the real-time layer, and IRQs at lower priorities to be treated as being in the non
real-time layer. The price paid is some additional complexity in the software and in
the VIC hardware.
Note
For either of the last two options, the new instructions speed up the IRQ re-enabling and
the stack changes that are likely to be required.
An abort can be caused by either:
• the MMU signalling an internal abort
• an external abort being raised from the AXI interfaces, by an AXI error response.
There are two types of abort:
• Prefetch Abort
• Data Abort on page 2-46.
IRQs are disabled when an abort occurs. When the aborts are configured to branch to Secure
Monitor mode, the FIQ is also disabled.
Note
The Interrupt Status Register shows at any time if there is a pending IRQ, FIQ, or External
Abort. For more information, see c12, Interrupt Status Register on page 3-123.
All aborts from the TLB are internal except for aborts from page table walks that are external
precise aborts. If the EA bit is 1 for translation aborts, see c1, Secure Configuration Register on
page 3-52, the core branches to Secure Monitor mode in the same way as it does for all other
external aborts.
Prefetch Abort
This is signaled with the Instruction as it enters the pipeline Decode stage.
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Programmer's Model
2-45