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22.9
Underflow exception
22.9.1
Exception enabled
22.9.2
Exception disabled
ARM DDI 0301H
ID012310
Underflow is detected pessimistically in non-RunFast mode. If the potential underflow is
confirmed by the support code for an operation with a floating-point result, an underflow
exception is generated. How this is confirmed depends on whether the VFP11 coprocessor is in
flush-to-zero mode.
If the FZ bit is set, all underflowing results are forced to a positive signed zero and written to the
destination register. The UFC flag is set in the FPSCR. No trap is taken. If the Underflow
exception enable bit is set, it is ignored.
If the FZ bit is not set what happens next depends on whether the Underflow exception is
enabled.
Setting the UFE bit, FPSCR[11], enables Underflow exceptions. The VFP11 coprocessor
detects most underflow conditions conclusively, but it detects some based on the possibility of
an underflow. The initial computation of the result exponent might be lower than a threshold for
the destination precision. In this case, the possibility of underflow because of massive
cancellation exists, but cannot be known in the first Execute stage. The VFP11 coprocessor
bounces on such cases and uses the support code to determine the exceptional status of the
operation. Underflow is confirmed if the result of the operation after rounding is less in
magnitude than the smallest normalized number in the destination format. If there is no
underflow, either catastrophic or to a subnormal result, the support code writes the computed
result to the destination register and returns without setting the UFC flag, FPSCR[3]. If there is
underflow, regardless of any accuracy loss, the intermediate result is written to the destination
register, UFC is set, and the Underflow user trap handler is called. The support code sets or
clears the IXC flag, FPSCR[4], as appropriate.
When the VFP11 coprocessor detects a potential underflow condition, the EX flag, FPEXC[31],
and the UFC flag, FPEXC[3], are set. The UFC flag in the FPSCR register is not set by the
hardware and must be set by the support code before calling the user trap handler. The source
and destination registers for the instruction are valid in the VFP11 register file. See section
Arithmetic exceptions on page 22-20 for the conditions that cause an underflow bounce.
Clearing the UFE bit, FPSCR[11], disables Underflow exceptions. When the FZ bit,
FPSCR[24], is not set, the VFP11 coprocessor bounces on potential underflow cases in the same
fashion as Exception enabled describes. The correct result is written to the destination register,
setting the appropriate exception flags.
When the FZ bit is set, the VFP11 coprocessor makes the determination of underflow before
rounding and flushes any result that underflows. A result that underflows returns a positive zero
to the destination register and sets the UFC flag, FPSCR[3].
Note
The determination of an underflow condition in flush-to-zero mode is made before rounding
rather than after. This means that the VFP11 coprocessor might not return the minimum normal
value when rounding would have produced it. Instead, it flushes to zero an intermediate value
with the minimum exponent for the destination precision, a fraction of all ones, and a round
increment. If the intermediate value was the minimum normal value before the underflow
condition test is made, it is not flushed to zero.
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VFP Exception Handling
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