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4.2.6
ARMv6 unaligned data access restrictions
ARM DDI 0301H
ID012310
The following restrictions apply for ARMv6 unaligned data access:
•
Accesses are not guaranteed atomic. They might be synthesized out of a series of aligned
operations in a shared memory system without guaranteeing locked transaction cycles.
•
Unaligned accesses loading the PC produce an alignment trap.
•
Accesses typically take a greater number of cycles to complete compared to a naturally
aligned transfer. The real-time implications must be carefully analyzed and key data
structures might require to have their alignment adjusted for optimum performance.
•
Accesses can abort on either or both halves of an access where this occurs over a page
boundary. The Data Abort handler must handle restartable aborts carefully after an
Alignment Fault status code is signaled.
As a result, shared memory schemes must not rely on seeing monotonic updates of non-aligned
data of loads, stores, and swaps for data items greater than byte width. Unaligned access
operations must not be used for accessing Device memory-mapped registers, and must be used
with care in Shared memory structures that are protected by aligned semaphores or
synchronization variables.
An Unalignment trap occurs if unaligned accesses to Strongly Ordered or Device when both:
•
the MMU is enabled, that is CP15 c1 bit 0, M bit, is 1
•
the Subpage AP bits are disabled, that is CP15 c1 bit 23, XP bit, is 1.
Swap and synchronization primitives, multiple-word or coprocessor access produce an
alignment fault regardless of the setting of the A bit.
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Unaligned and Mixed-endian Data Access Support
4-5
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