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3.2.25
c9, Data TCM Region Register
ARM DDI 0301H
ID012310
To use the Instruction and Data Cache Lockdown Registers read or write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c9
•
CRm set to c0
•
Opcode_2 set to:
—
0, for Data Cache
—
1, for Instruction Cache.
For example:
MRC p15, 0, <Rd>, c9, c0, 0
MCR p15, 0, <Rd>, c9, c0, 0
MRC p15, 0, <Rd>, c9, c0, 1
MCR p15, 0, <Rd>, c9, c0, 1
The system must only change a cache lockdown register when it is certain that all outstanding
accesses that might cause a cache line fill are complete. For this reason, the processor must
perform a Data Synchronization Barrier operation before the cache lockdown register changes,
see Data Synchronization Barrier operation on page 3-83.
The following procedure for lock down into a data or instruction cache way i, with N cache
ways, using Format C, ensures that only the target cache way i is locked down.
This is the architecturally defined method for locking data or instructions into caches:
1.
Ensure that no processor exceptions can occur during the execution of this procedure, by
disabling interrupts. If this is not possible, all code and data or instructions used by any
exception handlers that can be called must meet the conditions specified in step 2.
2.
Ensure that all data or instructions used by the following code, apart from the data or
instructions that are to be locked down, are either:
•
in an noncacheable area of memory, including the TCM
•
in an already locked cache way.
3.
Ensure that the data or instructions to be locked down are in a Cacheable area of memory.
4.
Ensure that the data or instructions to be locked down are not already in the cache, using
cache Clean and/or Invalidate instructions as appropriate, see c7, Cache operations on
page 3-69.
5.
Enable allocation to the target cache way by writing to the Instruction or Data Cache
Lockdown Register, with the CRm field set to 0, setting L equal to 0 for bit i and L equal
to 1 for all other ways.
6.
Ensure that the memory cache line is loaded into the cache by using an LDR instruction
to load a word from the memory cache line, for each of the cache lines to be locked down
in cache way i.
To lock down an instruction cache use the c7 Prefetch Instruction Cache Line operation
to fetch the memory cache line, see Invalidate, Clean, and Prefetch operations on
page 3-71.
7.
Write to the Instruction or Data Cache Lockdown Register, setting L to 1 for bit i and
restore all the other bits to the values they had before this routine was started.
The purpose of the Data TCM Region Register is to describe the physical base address and size
of the Data TCM region and to provide a mechanism to enable it.
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Non-Confidential, Unrestricted Access
; Read Data Cache Lockdown Register
; Write Data Cache Lockdown Register
; Read Instruction Cache Lockdown Register
; Write Instruction Cache Lockdown Register
System Control Coprocessor
3-89
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