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13.2
About the debug unit
13.2.1
Halting debug-mode debugging
13.2.2
Monitor debug-mode debugging
ARM DDI 0301H
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The processor debug unit assists in debugging software running on the processor. You can use
the processor debug unit, in combination with a software debugger program, to debug:
•
application software
•
operating systems
•
ARM processor based hardware systems.
The debug unit enables you to:
•
stop program execution
•
examine and alter processor and coprocessor state
•
examine and alter memory and input/output peripheral state
•
restart the processor core.
You can debug the processor in the following ways:
•
Halting debug-mode debugging
•
Monitor debug-mode debugging
•
Trace debugging. See Chapter 15 Trace Interface Port for interfacing with an ETM.
The processor debug interface is based on the IEEE Standard Test Access Port and
Boundary-Scan Architecture.
When the processor debug unit is in Halting debug-mode, the processor halts and enters Debug
state when a debug event, such as a breakpoint, occurs. When the processor is in Debug state,
an external host can examine and modify its state using the DBGTAP.
In Debug state you can examine and alter processor state, processor registers, coprocessor state,
memory, and input/output locations through the DBGTAP. This mode is intentionally invasive
to program execution. Halting debug-mode debugging requires:
•
external hardware to control the DBGTAP
•
a software debugger to provide the user interface to the debug hardware.
See CP14 c1, Debug Status and Control Register (DSCR) on page 13-7 to learn how to set the
processor debug unit into Halting debug-mode.
When the processor debug unit is in Monitor debug-mode, the processor takes a Debug
exception instead of halting. A special piece of software, a debug monitor target, can then take
control to examine or alter the processor state. Monitor debug-mode is essential in real-time
systems where the core cannot be halted to collect information. For example, engine controllers
and servo mechanisms in hard drive controllers that cannot stop the code without physically
damaging the components.
When debugging in Monitor debug-mode the processor stops execution of the current program
and starts execution of a debug monitor target. The state of the processor is preserved in the same
manner as all ARM exceptions. See the ARM Architecture Reference Manual on exceptions and
exception priorities. The debug monitor target communicates with the debugger to access
processor and coprocessor state, and to access memory contents and input/output peripherals.
Monitor debug-mode requires a debug monitor program to interface between the debug
hardware and the software debugger.
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Debug
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