Figure 3-38 Cache Operations - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
• implement the Wait For Interrupt clock control function.
Note
Cache operations also depend on:
• the C, W, I and RR bits, see c1, Control Register on page 3-44.
• the RA and RV bits, see c1, Auxiliary Control Register on page 3-48.
The following cache operations globally flush the BTAC:
• Invalidate Entire Instruction Cache
• Invalidate Both Caches.
c7 consists of one 32-bit register that performs 28 functions. Figure 3-38 shows the arrangement
of the 24 functions in this group that operate with the MCR and MRC instructions.
CRn Opcode_1 CRm
c7 0 c0
c4
c5
c6
c7
c8
c10
c13
c14
Read-only
Figure 3-39 on page 3-71 shows the arrangement of the 4 functions in this group that operate
with the MCRR instruction.
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Opcode_2
4 Wait For Interrupt (WFI)
SBZ
0 PA Register
0 Invalidate Entire Instruction Cache
SBZ
1 Invalidate Instruction Cache Line (using MVA)
MVA
2 Invalidate Instruction Cache Line (using Index)
Index
4 Flush Prefetch Buffer
SBZ
6 Flush Entire Branch Target Cache
SBZ
7 Flush Branch Target Cache Entry
MVA
0 Invalidate Entire Data Cache
SBZ
1 Invalidate Data Cache Line (using MVA)
MVA
2 Invalidate Data Cache Line (using Index)
Index
0 Invalidate Both Caches
SBZ
0-3 VA to PA Translation in the current world
4-7 VA to PA Translation in the other world
0 Clean Entire Data Cache
SBZ
1 Clean Data Cache Line (using MVA)
MVA
2 Clean Data Cache Line (using Index)
Index
4 Data Synchronization Barrier (DSB)
SBZ
5 Data Memory Barrier (DMB)
SBZ
6 Cache Dirty Status Register
1 Prefetch Instruction Cache Line
MVA
0 Clean and Invalidate Entire Data Cache
SBZ
1 Clean and Invalidate Data Cache Line (using MVA)
MVA
2 Clean and Invalidate Data Cache Line (using Index)
Index
Read/write Write only
Should Be Zero
SBZ
Using MVA
MVA
Using Set and Index
Index
System Control Coprocessor
Accessible in User mode

Figure 3-38 Cache operations

3-70