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ARM DDI 0301H
ID012310
The Secure Monitor can poll these bits to detect the exceptions before it completes context
switches. This can reduce interrupt latency.
To use the Interrupt Status Register read CP15 with:
•
Opcode_1 set to 0
•
CRn set to c12
•
CRm set to c1
•
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c12, c1, 0
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; Read Interrupt Status Register
System Control Coprocessor
3-125
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