Table of Contents
Advertisement
13.10 Debug state
ARM DDI 0301H
ID012310
When the conditions in Behavior of the processor on debug events on page 13-33 are met then
the processor switches to Debug state. While in Debug state, the processor behaves as follows:
•
The DSCR[0] core halted bit is set.
The DBGACK signal is asserted, see External signals on page 13-52.
•
•
The DSCR[5:2] method of entry bits are set appropriately.
•
The CP15 IFSR, DFSR, FAR, and WFAR registers are set as Effect of a debug event on
CP15 registers on page 13-34 describes.
•
The processor is halted. The pipeline is flushed and no instructions are fetched.
•
The processor does not change the execution mode. The CPSR is not altered.
•
The DMA engine keeps on running. The DBGTAP debugger can stop it and restart it using
CP15 operations if it has permission to do so. See Chapter 7 Level One Memory System
for details.
•
Interrupts and exceptions are treated as Interrupts on page 13-39 and Exceptions on
page 13-39 describe.
•
Software debug events are ignored.
•
The external debug request signal is ignored.
•
Debug state entry request commands are ignored.
•
There is a mechanism, using the Debug Test Access Port, where the core is forced to
execute an ARM state instruction. This mechanism is enabled using DSCR[13] execute
ARM instruction enable bit.
•
The core executes the instruction as if it is in ARM state, regardless of the actual value of
the T and J bits of the CPSR.
•
Any instruction issued in Debug state that puts the processor into a mode or state where
debug is not permitted is ignored.
•
When in Debug state the CPSR must be modified using the MSR instruction.
•
In Debug state MSR can be used to modify the CPSR mode bits from any mode to any
mode that is permitted by the debug level set by SPIDEN and SUIDEN.
For example, if SPIDEN is set, the CPSR mode bits can be altered to change to Secure
Monitor mode from any mode, including all Non-secure modes.
The CPSR mode can be altered from Non-secure User mode to any Non-secure Privileged
mode regardless of the state of SPIDEN.
•
Instructions that write to the I, F, and A bits of the CPSR are ignored when:
—
debug is only permitted in Non-secure world and in Secure User mode, SPIDEN=0,
SUIDEN=1
—
the processor is in Secure user mode
•
The MSR instruction can also be used to alter the J and T execution state bits of the CPSR.
•
The PC behaves as Behavior of the PC in Debug state on page 13-38 describes.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Debug
13-37
Hide quick links:
Advertisement
Table of Contents
