ARM Cortex-M3 Technical Reference Manual
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ARM Cortex-M3 Technical Reference Manual

R2p0
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Cortex
-M3
™
r2p0
Technical Reference Manual
Copyright © 2005-2008 ARM Limited. All rights reserved.
ARM DDI 0337G

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Summary of Contents for ARM Cortex-M3

  • Page 1 Cortex ™ r2p0 Technical Reference Manual Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
  • Page 3 Product Status The information in this document is Final (information on a developed product). Web Address http://www.arm.com ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Confidential Unrestricted Access...
  • Page 4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Unrestricted Access...

  • Page 5: Table Of Contents

    About the programmer’s model ..............2-2 Privileged access and user access ............. 2-3 Registers ..................... 2-4 Data types ....................2-10 Memory formats ..................2-11 Instruction set summary ................2-13 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 6 MPU programmer’s model ................9-3 MPU access permissions ................. 9-13 MPU aborts ....................9-15 Updating an MPU region ................9-16 Interrupts and updating the MPU .............. 9-19 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 7 Chapter 15 Embedded Trace Macrocell Interface 15.1 About the ETM interface ................15-2 15.2 CPU ETM interface port descriptions ............15-3 15.3 Branch status interface ................15-6 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 8 ETM interface ................... A-14 A.13 AHB Trace Macrocell interface ..............A-16 A.14 Test interface .................... A-17 A.15 WIC interface .................... A-18 Appendix B Revisions Glossary viii Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 9 Table 5-1 Exception types ......................5-4 Table 5-2 Priority-based actions of exceptions ................. 5-6 Table 5-3 Priority grouping ......................5-8 Table 5-4 Exception entry steps ....................5-12 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 10 Table 8-29 Auxiliary Fault Status Register bit assignments ............8-42 Table 8-30 Software Trigger Interrupt Register bit assignments ..........8-42 Table 9-1 MPU registers ......................9-3 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 11 AHB-AP Transfer Address Register bit assignments ..........11-42 Table 11-31 AHB-AP Data Read/Write Register bit assignments ..........11-43 Table 11-32 AHB-AP Banked Data Register bit assignments ........... 11-43 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 12 Table 19-5 PPB input port timing parameters ................19-4 Table 19-6 Debug input ports timing parameters ..............19-4 Table 19-7 Test input ports timing parameters ................. 19-5 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 13 WIC interface signals ....................A-18 Table B-1 Differences between issue E and issue F ..............B-1 Table B-2 Differences between issue F and issue G ..............B-5 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xiii Non-Confidential Unrestricted Access...
  • Page 14 List of Tables Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 15 Power-on reset ......................6-6 Figure 6-3 Internal reset synchronization ................... 6-7 Figure 7-1 SLEEPING power control example ................7-4 Figure 7-2 SLEEPDEEP power control example ................ 7-5 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 16 WIC mode enable sequence ..................7-7 Figure 7-4 Power down timing sequence ................... 7-8 Figure 7-5 PMU, WIC, and Cortex-M3 interconnect ..............7-9 Figure 8-1 Interrupt Controller Type Register bit assignments ..........8-7 Figure 8-2 Auxiliary Control Register bit assignments ............... 8-8 Figure 8-3 SysTick Control and Status Register bit assignments ..........
  • Page 17 Figure 17-14 Dedicated pin used for TRACESWO ..............17-21 Figure 17-15 SWO shared with TRACEPORT ................17-22 Figure 17-16 SWO shared with JTAG-TDO ................17-22 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xvii Non-Confidential Unrestricted Access...
  • Page 18 List of Figures xviii Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 19 Preface This preface introduces the Cortex-M3 Technical Reference Manual (TRM). It contains the following sections: • About this book on page xx • Feedback on page xxv. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 20: Preface

    Preface About this book This book is for the Cortex-M3 processor. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: Identifies the major revision of the product. Identifies the minor revision or modification status of the product.
  • Page 21 Read this for a description of the processor Advanced High-performance Bus (AHB) trace macrocell interface. Chapter 18 Instruction Timing Read this for a description of the processor instruction timing and clock cycles. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 22 < and > Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> xxii Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 23: Key To Timing Diagram Conventions

    Denotes AXI write address channel signals. Prefix B Denotes AXI write response channel signals. Prefix C Denotes AXI low-power interface signals. Prefix H Denotes Advanced High-performance Bus (AHB) signals. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. xxiii Non-Confidential Unrestricted Access...
  • Page 24 Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Further reading This section lists publications by ARM and by third parties. for access to ARM documentation. http://infocenter.arm.com ARM publications This book contains information that is specific to this product. See the following documents for other relevant information: •...

  • Page 25: Feedback

    Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.
  • Page 26 Preface xxvi Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 27 Execution pipeline stages on page 1-12 • Prefetch Unit on page 1-14 • Branch target forwarding on page 1-15 • Store buffers on page 1-18 • Product revisions on page 1-19. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 28: Chapter 1 Introduction

    Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. • Memory Protection Unit (MPU). An optional MPU for memory protection: — Eight memory regions. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 29 Instrumentation Trace Macrocell (ITM) for support of printf style debugging. — Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA). — Optional Embedded Trace Macrocell (ETM) for instruction trace. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 30: Components, Hierarchy, And Implementation

    Interrupts on page 1-11 • Observation on page 1-11 • ROM table on page 1-11. Figure 1-1 on page 1-5 shows the structure of the processor. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 31: Figure 1-1 Cortex-M3 Block Diagram

    32-bit. See the ARMv7-M Architecture Reference Manual for more information. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single cycle 32-bit multiply. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 32 Thumb 32-bit instruction with one Thumb instruction, or the lower/upper halfword of another halfword-aligned Thumb 32-bit instruction. All fetch addresses from the core are word aligned. If Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...
  • Page 33 PPB. This is for data load/stores and debug accesses to PPB space. This is a 32-bit APB (v3.0) bus. The bus matrix also controls the following: • Unaligned accesses. The bus matrix converts unaligned processor accesses into aligned accesses. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 34 1.2.6 You can configure the implementation to contain an ITM. The ITM is a an application driven trace source that supports application event trace and printf style debugging. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...
  • Page 35 1.2.11 TPIU You can configure the system at implementation to include an TPIU. The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, an ETM if present, and an off-chip Trace Port Analyzer. ARM DDI 0337G Copyright ©...
  • Page 36 • In a production device, the TPIU might have been removed. Note There is no Cortex-M3 trace capability if the TPIU is removed. Chapter 17 Trace Port Interface Unit describes the TPIU. 1.2.12 You can configure the implementation to include a Wake-up Interrupt Controller (WIC).

  • Page 37: Table

    The ROM table is modified from that described in ROM memory table on page 4-7 if: • additional debug components have been added into the system • all debug functionality has been removed from the implementation. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-11 Non-Confidential Unrestricted Access...

  • Page 38: Execution Pipeline Stages

    Instruction Divide Decode Fetch Register Read Shift Branch Branch Branch forwarding and speculation ALU branch not forwarded/speculated LSU branch result Figure 1-2 Cortex-M3 pipeline stages 1-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 39 AHB interface, multiply/divide, and ALU with branch result. The pipeline structure provides a pipelined 2-cycle memory access with no ALU usage penalty, address generation forwarding for pointer indirection. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-13 Non-Confidential Unrestricted Access...

  • Page 40: Prefetch Unit

    Short subroutine returns are optimized to take advantage of the forwarding behavior in the case of BX LR. 1-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 41: Branch Target Forwarding

    A refinement is to only predict backward conditional branches to accelerate loops. Alternatively, with ARM compilers favouring loops with unconditional branch backwards at the bottom and then conditional branch forward tests on the loop limit, the core fetch queue being ahead at the start of the loop yields good behavior.
  • Page 42 BRCHSTAT[3] status of the conditional execution can mask the external mispredict on the output of the controller's registered system interface, appearing as an idle cycle. 1-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 43 A 128-bit interface is better at this point. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-17 Non-Confidential...

  • Page 44: Store Buffers

    Introduction Store buffers The processor contains two store buffers: • Cortex-M3 core LSU store buffer for immediate offset opcode. • Bus-matrix store buffer for wait states and unaligned transactions. The core store buffer optimizes the case of STR rx,[ry,#imm], which is common in compiled code.

  • Page 45: Product Revisions

    CPUID Base Register VARIANT field changed to indicate Rev1. See NVIC register descriptions on page 8-7. • Cortex-M3 Rev0 Bit-band accesses in BE8 mode required access sizes to be byte. Cortex-M3 Rev1 has been changed so that BE8 bit-band accesses function with any access size.

  • Page 46: About The Dp

    New implementation option to enable the resetting of all registers within the processor. • Architectural clock gating inclusion is now controlled using one implementation option. 1-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 47 — stop IT folding — disable the write buffers in Cortex-M3 for default memory map accesses. For details on the Auxiliary Control Register see Auxiliary Control Register on page 8-8. • The STKALIGN bit reset value in the Configuration and Control Register at...
  • Page 48 Introduction 1-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 49 Privileged access and user access on page 2-3 • Registers on page 2-4 • Data types on page 2-10 • Memory formats on page 2-11 • Instruction set summary on page 2-13. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 50: Chapter 2 Programmer's Model

    The processor implements the ARMv7-M architecture. This includes all the 16-bit Thumb instructions and the base 32-bit Thumb instructions. The processor cannot execute ARM instructions. For more information about the ARMv7-M Thumb instruction set see the ARMv7-M Architecture Reference Manual.

  • Page 51: Privileged Access And User Access

    It is also possible to switch from main stack to process stack while in Thread mode by writing to CONTROL[1] using the MSR instruction, in addition to being selectable using the EXC_RETURN value from an exit from Handler mode. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 52: Registers

    High registers Registers r8-r12 are accessible by all 32-bit instructions that specify a general-purpose register. Registers r8-r12 are not accessible by all 16-bit instructions. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 53 You can access the APSR with the MSR(2) and MRS(2) instructions. Figure 2-2 on page 2-6 shows the bit assignments of the APSR. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 54: Table 2-1 Application Program Status Register Bit Assignments

    The Interrupt PSR (IPSR) contains the Interrupt Service Routine (ISR) number of the current exception activation. Figure 2-2 shows the bit assignments of the IPSR. Reserved ISR NUMBER Figure 2-3 Interrupt Program Status Register bit assignments Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 55: Table 2-2 Interrupt Program Status Register Bit Assignments

    If-then state field The IT field of the EPSR contain the execution state bits for the If-Then instruction. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 56: Table 2-3 Bit Functions Of The Epsr

    0. It can also be cleared by unstacking from an exception where the stacked T bit is 0. Executing an instruction while the T bit is clear causes an INVSTATE exception. [23:16] Reserved. [9:0] Reserved. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 57 Configuration Control Register. This information is stored in bit [9] of the xPSR on the stack, and it is a 1 if the stack was forced to be 8-byte aligned. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 58: Data Types

    Note Memory systems are expected to support all data types. In particular, the system must support subword writes without corrupting neighboring bytes in that word. 2-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 59: Memory Formats

    It always accesses code in little-endian format. Note Little-endian is the default memory format for ARM processors. In little-endian format, the byte with the lowest address in a word is the least-significant byte of the word. The byte with the highest address in a word is the most significant.

  • Page 60: Figure 2-5 Little-Endian And Big-Endian Memory Formats

    3 address 2 address 1 address 0 Halfword 0 at address 2 Halfword 1 at address 0 Figure 2-5 Little-endian and big-endian memory formats 2-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 61: Instruction Set Summary

    • a summary of the processor 16-bit instructions • a summary of the processor 32-bit instructions. Table 2-4 lists the 16-bit Cortex-M3 instructions. Table 2-4 16-bit Cortex-M3 instruction summary Operation Assembler Add register value and C flag to register value ADC <Rd>, <Rm>...
  • Page 62 Programmer’s Model Table 2-4 16-bit Cortex-M3 instruction summary (continued) Operation Assembler Compare negation of register value with another register value CMN <Rn>, <Rm> Compare immediate 8-bit value CMP <Rn>, #<immed_8> Compare registers CMP <Rn>, <Rm> Compare high register to low or high register CMP <Rn>, <Rm>...
  • Page 63 Programmer’s Model Table 2-4 16-bit Cortex-M3 instruction summary (continued) Operation Assembler Move immediate 8-bit value to register MOV <Rd>, #<immed_8> Move low register value to low register MOV <Rd>, <Rn> Move high or low register value to high or low register MOV <Rd>, <Rm>...

  • Page 64: Table 2-5 32-Bit Cortex-M3 Instruction Summary

    Programmer’s Model Table 2-4 16-bit Cortex-M3 instruction summary (continued) Operation Assembler Store register halfword [15:0] to register address + register offset STRH <Rd>, [<Rn>, <Rm>] Subtract immediate 3-bit value from register SUB <Rd>, <Rn>, #<immed_3> Subtract immediate 8-bit value from register value SUB <Rd>, #<immed_8>...
  • Page 65 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Conditional branch B{cond}.W <label> Clear bit field BFC.W <Rd>, #<lsb>, #<width> Insert bit field from one register value into another BFI.W <Rd>, <Rn>, #<lsb>, #<width> Bitwise AND register value with complement of immediate BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>...
  • Page 66 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Memory word from base register address + immediate 12-bit LDR.W <Rxf>, [<Rn>, #<offset_12>] offset Memory word to PC from register address + immediate 12-bit LDR.W PC, [<Rn>, #<offset_12>] offset Memory word to PC from base register address immediate LDR.W PC, [Rn], #<+/-<offset_8>...
  • Page 67 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Load register exclusive calculates an address from a base LDREX<c> <Rt>,[<Rn>{,#<imm>}] register value and an immediate offset, loads a word from memory, writes it to a register Load register exclusive halfword calculates an address from a LDREXH<c>...
  • Page 68 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Memory signed halfword [15:0] from base register address LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>] immediate 8-bit offset, preindexed Memory signed halfword [15:0] from register address shifted LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]...
  • Page 69 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Reverse bytes in each halfword REV16.W <Rd>, <Rn> Reverse bytes in bottom halfword and sign-extend REVSH.W <Rd>, <Rn> Rotate right by number in register ROR{S}.W <Rd>, <Rn>, <Rm> Rotate right with extend RRX{S}.W <Rd>, <Rm>...
  • Page 70 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Register byte [7:0] to register address immediate 8-bit offset, STRB.W <Rxf>, [<Rn>], #+/–<offset_8> postindexed Register byte [7:0] to register address shifted by 0, 1, 2, or 3 STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]...
  • Page 71 Programmer’s Model Table 2-5 32-bit Cortex-M3 instruction summary (continued) Operation Assembler Table branch byte TBB [<Rn>, <Rm>] Table branch halfword TBH [<Rn>, <Rm>, LSL #1] Exclusive OR register value with immediate 12-bit value TEQ.W <Rn>, #<modify_constant(immed_12)> Exclusive OR register value with shifted register value TEQ.W <Rn>, <Rm>{, <shift}...
  • Page 72 Programmer’s Model 2-24 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 73: Chapter 3 System Control

    Chapter 3 System Control This chapter describes the registers that program the processor. It contains the following section: • Summary of processor registers on page 3-2. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 74: Summary Of Processor Registers

    Irq 0 to 31 Set Enable Register Read/write 0xE000E100 0x00000000 Irq 224 to 239 Set Enable Register Read/write 0xE000E11C 0x00000000 Irq 0 to 31 Clear Enable Register Read/write 0xE000E180 0x00000000 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 75 Irq 236 to 239 Priority Register Read/write 0xE000E4EC 0x00000000 CPUID Base Register Read-only 0xE000ED00 0x412FC230 Interrupt Control State Register Read/write or read-only 0xE000ED04 0x00000000 Vector Table Offset Register Read/write 0xE000ED08 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 76 ISAR0: ISA Feature register0 Read-only 0xE000ED60 0x01141110 ISAR1: ISA Feature register1 Read-only 0xE000ED64 0x02111000 ISAR2: ISA Feature register2 Read-only 0xE000ED68 0x21112231 ISAR3: ISA Feature register3 Read-only 0xE000ED6C 0x01111110 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 77: Core Debug Registers

    Read/Write 0xE000EDF0 0x00000000 Debug Core Register Selector Register Write-only 0xE000EDF4 Debug Core Register Data Register Read/Write 0xE000EDF8 Debug Exception and Monitor Control Register. Read/Write 0xE000EDFC 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 78: Table 3-3 Flash Patch Register Summary

    Value 0x04 PID5 Read-only 0xE0002FD4 Value 0x00 PID6 Read-only 0xE0002FD8 Value 0x00 PID7 Read-only 0xE0002FDC Value 0x00 PID0 Read-only 0xE0002FE0 Value 0x03 PID1 Read-only 0xE0002FE4 Value 0xB0 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 79: Table 3-4 Dwt Register Summary

    0xE000101C DWT_COMP0 Read/write DWT Comparator Register 0xE0001020 DWT_MASK0 Read/write DWT Mask Registers 0xE0001024 DWT_FUNCTION0 Read/write DWT Function Registers 0xE0001028 0x00000000 DWT_COMP1 Read/write DWT Comparator Register 0xE0001030 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 80 0x00 0x00 CID0 Read-only Value 0xE0001FF0 0x0D 0x0D CID1 Read-only 0xE0001FF4 0xE0 Value 0xE0 CID2 Read-only 0xE0001FF8 0x05 Value 0x05 CID3 Read-only Value 0xE0001FFC 0xB1 0xB1 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 81: Table 3-5 Itm Register Summary

    0xE0000FE4 0x000000B0 PID2 Read-only 0xE0000FE8 0x0000002B PID3 Read-only 0xE0000FEC 0x00000000 CID0 Read-only 0xE0000FF0 0x0000000D CID1 Read-only 0xE0000FF4 0x000000E0 CID2 Read-only 0xE0000FF8 0x00000005 CID3 Read-only 0xE0000FFC 0x000000B1 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 82: Table 3-6 Ahb-Ap Register Summary

    SW-DP Description ABORT The Abort Register IDCODE The Identification Code Register CTRL/STAT The Control/Status Register SELECT The AP Select Register RDBUFF The Read Buffer Register 3-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 83: Table 3-8 Mpu Registers

    MPU Alias 2 Region Attribute and Size register Alias of 0xE000EDB0 MPU Alias 3 Region Base Address register Alias of 0xE000EDB4 MPU Alias 3 Region Attribute and Size register Alias of 0xE000EDB8 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-11 Non-Confidential Unrestricted Access...

  • Page 84: Table 3-9 Tpiu Registers

    PID6 Read only 0xE0040FD8 0x00 PID7 Read only 0xE0040FDC 0x00 PID0 Read only 0xE0040FE0 0x23 PID1 Read only 0xE0040FE4 0xB9 PID2 Read only 0xE0040FE8 0x2B 3-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 85: Table 3-10 Etm Registers

    TraceEnable Control 1 Write-only 0xE0041024 FIFOFULL Region Write-only 0xE0041028 FIFOFULL Level Write-only or read/write 0xE004102C ViewData Write-only 0xE0041030-0xE004103C Address Comparators Write-only 0xE0041040- 0xE004113C Counters Write-only 0xE0041140-0xE004157C ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-13 Non-Confidential Unrestricted Access...
  • Page 86 0xE0041FB8 Device Type Read-only 0xE0040FCC Peripheral ID 4 Read-only 0xE0041FD0 Peripheral ID 5 Read-only 0xE0041FD4 Peripheral ID 6 Read-only 0xE0041FD8 Peripheral ID 7 Read-only 0xE0041FDC 3-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 87 Peripheral ID 3 Read-only 0xE0041FEC Component ID 0 Read-only 0xE0041FF0 Component ID 1 Read-only 0xE0041FF4 Component ID 2 Read-only 0xE0041FF8 Component ID 3 Read-only 0xE0041FFC ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-15 Non-Confidential Unrestricted Access...
  • Page 88 System Control 3-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 89: Chapter 4 Memory Map

    This chapter describes the processor fixed memory map and its bit-banding feature. It contains the following sections: • About the memory map on page 4-2 • Bit-banding on page 4-5 • ROM memory table on page 4-7. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 90: About The Memory Map

    Bit band alias 31MB 0.5GB Peripheral Bit band region 0.5GB SRAM 32MB Bit band alias 31MB 0.5GB Code Bit band region Figure 4-1 Processor memory map Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 91: Table 4-1 Memory Interfaces

    System System segment for vendor system peripherals. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 92: Table 4-2 Memory Region Permissions

    Private Peripheral Bus and System space at are permanently 0xE0000000 - 0xFFFFFFFF XN. The MPU cannot change this. For a description of the processor bus interfaces, see Chapter 12 Bus Interface. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 93: Bit-Banding

    + (0*32) + 0 *4. • The alias word at 0x2200001C maps to bit [7] of the bit-band byte at 0x20000000 ) + 7*4. 0x2200001C 0x22000000 0*32 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 94: Figure 4-2 Bit-Band Mapping

    Bits [31:1] are zero. 4.2.2 Directly accessing a bit-band region You can directly access the bit-band region with normal reads and writes, and writes to that region. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 95: Rom Memory Table

    DAP. Bit [0] is clear when only debug resources are accessible using the DAP. PID4 0xFD0 PID5 0xFD4 PID6 0xFD8 PID7 0xFDC 0xFE0 PID0 0xFE4 PID1 PID2 0xFE8 PID3 0xFEC CID0 0xFF0 0x0D ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 96 Memory Map Table 4-3 ROM table (continued) Offset Value Name Description CID1 0xFF4 0x10 CID2 0xFF8 0x05 CID3 0xFFC 0xB1 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 97 Exception control transfer on page 5-24 • Setting up multiple stacks on page 5-25 • Abort model on page 5-27 • Activation levels on page 5-32 • Flowcharts on page 5-34. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 98: Chapter 5 Exceptions

    Configurable number of interrupt priorities, from 3 to 8 bits (8 to 256 levels). • Separate stacks and privilege levels for Handler and Thread modes. • ISR control transfer using the calling conventions of the C/C++ standard ARM Architecture Procedure Call Standard (AAPCS). • Priority masking to support critical regions.
  • Page 99 Software can choose only to enable a subset of the configured number of interrupts, and can choose how many bits of the configured priorities to use. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 100: Exception Types

    This is synchronous when precise and asynchronous when imprecise. Usage Fault Usage fault, such as Undefined instruction executed or Configurable illegal state transition attempt. This is synchronous. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 101 NVIC priority value of 0 to N, where N is the largest priority value implemented. Internally, the highest user-settable priority (0) is treated as 4. You can enable or disable this fault. See System Handler Control and State Register bit assignments on page 8-30. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 102: Exception Priority

    In the processor exception model, priority determines when and how the processor takes exceptions. You can: • assign software priority levels to interrupts • group priorities by splitting priority levels into pre-emption priorities and subpriorities. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 103 This is consistent with the priority precedence scheme. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 104: Table 5-3 Priority Grouping

    For more information on priority optimizations, priority level grouping, and priority masking, see the ARMv7-M Architecture Reference Manual. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 105: Privilege And Stacks

    For a basic protected thread model, the user threads run in Thread mode using the process stack, and the kernel and the interrupts run privileged using the main stack. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 106 Access rules to memory locations based on an MPU. When fitted with an MPU, the access restrictions can control what memory can be read, written, and executed. Only Thread mode can be unprivileged. All exceptions are privileged. 5-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 107: Pre-Emption

    Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-11 Non-Confidential...

  • Page 108: Table 5-4 Exception Entry Steps

    EXC_RETURN is one of 16 values as defined in ARMv7-M Architecture Reference Manual. a. When tail-chaining, this step is skipped. Figure 5-2 on page 5-13 shows an example of exception entry timing. 5-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 109: Figure 5-2 Exception Entry Timing

    (3'b001). Prior to that it indicates which ISR is being fetched. Figure 5-2 shows that there is a 12-cycle latency from asserting the interrupt to the first instruction of the ISR executing. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-13 Non-Confidential Unrestricted Access...

  • Page 110: Tail-Chaining

    ETMINTNUM remains asserted throughout the duration of the ISR. Figure 5-3 shows that there is a 6-cycle latency when returning from the last ISR to executing the new ISR. 5-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 111: Late-Arriving

    INTISR[8] can pre-empt before the first instruction of the ISR for INTISR[2] enters Execute stage. A higher priority interrupt after that point is managed as a pre-emption. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-15 Non-Confidential Unrestricted Access...
  • Page 112 ISR. • ETMINTNUM[8:0] indicates the number of the active interrupt. ETMINTNUM remains asserted throughout the duration of the ISR. 5-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 113: Exit

    Because of dynamic priority changes, the NVIC uses interrupt numbers instead of interrupt priorities to determine which ISR is current. Figure 5-5 on page 5-18 shows an example of exception exit timing. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-17 Non-Confidential Unrestricted Access...

  • Page 114: Figure 5-5 Exception Exit Timing

    Exception returns occur when one of the following instructions loads a value of into the PC: 0xFFFFFFFX • POP/LDM which includes loading the PC • LDR with PC as a destination • BX with any register. 5-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 115: Table 5-6 Exception Return Behavior

    This address range is defined to have Execute Never (XN) permissions, and results in a MemManage fault. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-19 Non-Confidential Unrestricted Access...

  • Page 116: Resets

    An example of a full vector table: unsigned int stack_base[STACK_SIZE]; void ResetISR(void); void NmiISR(void); … ISR_VECTOR_TABLE vector_table_at_0 stack_base + sizeof(stack_base), ResetISR, NmiSR, FaultISR, 5-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 117: Table 5-8 Reset Boot-Up Behavior

    I2CIsr Note Vector table entries are ARM/Thumb interworking compatible. This causes bit [0] of the vector value to load into the EPSR T-bit on exception entry. Creating a table entry with bit [0] clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector.
  • Page 118 // do setup work (initialize variables, initialize runtime if wanted, setup peripherals, etc) nvic[INT_ENA] = 1; // enable interrupts nvic_regs[NV_SLEEP] |= NVSLEEP_ON_EXIT; // will not normally come back after 1st exception while (1) wfi(); 5-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 119 Thread mode is used for the user code for Real Time Operating System (RTOS) models using threads and privilege. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-23 Non-Confidential Unrestricted Access...

  • Page 120: Exception Control Transfer

    Exception postamble If the new exception has higher priority than the stacked exception to which the processor is returning, the processor tail-chains the new exception. 5-24 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 121: Setting Up Multiple Stacks

    ; return from Handler to Thread Example 5-5 on page 5-26 shows how to implement a simple context switcher after the switch to Thread on PSP. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-25 Non-Confidential Unrestricted Access...
  • Page 122 Thread from MSP to PSP can be made, or the non-stacked registers can be guaranteed not to have been modified by a stacked Handler, is when there is only one active ISR/Handler. 5-26 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 123: Abort Model

    A local fault handler causes a fault with the same or higher priority. • An exception handler causes a fault with the same or higher priority. • The local fault is not enabled. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-27 Non-Confidential Unrestricted Access...

  • Page 124: Table 5-10 Faults

    Precise data bus error PRECISERR BusFault Bus error returned because of data BUSERR access, and was precise, points to instruction. 5-28 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 125 This can be enabled to occur when CHKERR SDIV or UDIV is executed with a divisor of 0, and the DIV_0_TRP bit is set. SVCall System request (Service Call). ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-29 Non-Confidential Unrestricted Access...

  • Page 126: Table 5-11 Debug Faults

    BFAR and MFAR are the same physical register. Because of this, the BFARVALID and MFARVALID bits are mutually exclusive. Table 5-12 on page 5-31 shows the fault status registers and two fault address registers. 5-30 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 127: Table 5-12 Fault Status And Fault Address Registers

    Escalation and Special MMSR Mem Manage MMAR MPU faults BFSR Bus Fault BFAR Bus faults UFSR Usage Fault Usage fault DFSR Debug Monitor or Halt Debug traps ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-31 Non-Confidential Unrestricted Access...

  • Page 128: Activation Levels

    Debug event when halting not enabled Synchronous Privileged Main SVC instruction External interrupt a. Interrupt service routine. b. Nonmaskable interrupt. c. Coprocessor. d. Software interrupt. 5-32 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 129: Table 5-15 Exception Subtype Transitions

    Boosts priority of local handler to same as hard fault so it can Configurable fault return and chain to Configurable Fault handler handler a. While halting not enabled. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-33 Non-Confidential Unrestricted Access...

  • Page 130: Flowcharts

    PC at return location? active interrupt? Pre-empt Pending interrupt higher priority than stacked interrupt? Return from interrupt Figure 5-6 Interrupt handling flowchart 5-34 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 131: Figure 5-7 Pre-Emption Flowchart

    Figure 5-8 on page 5-36 shows how the processor restores the stacked ISR or tail-chains to a late-arriving interrupt with higher priority than the stacked ISR. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-35 Non-Confidential Unrestricted Access...

  • Page 132: Figure 5-8 Return From Interrupt Flowchart

    Read new PC from vector table Popped last register? Fill pipeline from PC Execute instructions Adjust stack, load pipeline from PC Execute instructions Figure 5-8 Return from interrupt flowchart 5-36 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 133: Chapter 6 Clocking And Resets

    This chapter describes the processor clocking and resets. It contains the following sections: • Clocking on page 6-2 • Resets on page 6-4 • Cortex-M3 reset modes on page 6-5. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 134: Clocking

    SW-DP. It is asynchronous to the other clocks. TRACECLKIN is the reference clock for the Trace Port Interface Unit (TPIU). It is asynchronous to the other clocks. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...
  • Page 135 The processor also contains a STCLK input. This port is not a clock. It is a reference input for the SysTick counter, and it must be less than half the frequency of FCLK. STCLK is synchronized internally by the processor to FCLK. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 136: Resets

    Instrumentation Trace Macrocell (ITM) • AHB-AP. nTRST SWJ-DP reset Note nTRST resets SWJ-DP. If your implementation does not contain SWJ-DP, this reset must be tied off. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 137: Cortex-M3 Reset Modes

    Reset of SWJ-DP logic. Note PORESETn resets a superset of the SYSRESETn logic. 6.3.1 Power-on reset Figure 6-1 on page 6-6 shows the reset signals for the macrocell. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 138: Figure 6-1 Reset Signals

    It is recommended that you assert the reset signals for at least three HCLK cycles to ensure correct reset behavior. Figure 6-3 on page 6-7 shows the internal reset synchronization. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 139: Figure 6-3 Internal Reset Synchronization

    Clocking and Resets Note You must consider LOCKUP from the Cortex-M3 system for inclusion in any external watchdog circuitry when an external debugger is not attached. CortexM3Integration HCLK CortexM3 PORESETn, SYSRESETn RSTBYPASS Figure 6-3 Internal reset synchronization 6.3.2 System reset A system or warm reset initializes the majority of the macrocell, excluding the NVIC debug logic, FPB, DWT, and ITM.
  • Page 140 Normal operation During normal operation, neither processor reset nor power-on reset is asserted. If the SWJ-DP port is not being used, the value of nTRST does not matter. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 141: Chapter 7 Power Management

    This chapter describes the processor power management functions. It contains the following sections: • About power management on page 7-2 • System power management on page 7-3. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 142: About Power Management

    The ARMv7-M architecture supports system sleep modes that can stop the Cortex-M3 and system clocks for greater power reductions. These are described in System power management on page 7-3.

  • Page 143: System Power Management

    Power Management System power management Writing to the System Control Register (see System Control Register on page 8-25) controls the Cortex-M3 system power states. Table 7-1 shows the supported sleep modes. Table 7-1 Supported sleep modes Sleep mechanism Description Sleep-now The Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions request the sleep-now model.

  • Page 144: Figure 7-1 Sleeping Power Control Example

    Suppressing HCLK using the clock-gating scheme in Figure 7-1 prevents debug accesses. The CoreSight Debug Ports (DPs) provide a power up signal that enables the system to bypass the clock-gating logic in Figure 7-1. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 145: Figure 7-2 Sleepdeep Power Control Example

    SLEEPDEEP in the low-power state. When exiting low-power state, the LOCK signal indicates that the PLL is stable, and it is safe to enable the Cortex-M3 clock, ensuring that the processor is not re-started until the clocks are stable. Cortex M3 processor...
  • Page 146 WIC functionality. WIC overview The Cortex-M3 NVIC has logic dedicated to determining whether at any point in time a newly received interrupt is of higher priority than the current priority and must therefore be taken over the current execution context or priority. This priority scheme also operates during WFE, WFI, and sleep-on-exit to determine when the core must resume execution of instructions after sleeping.

  • Page 147: Figure 7-3 Wic Mode Enable Sequence

    Figure 7-4 on page 7-8 shows an example of the previously described functionality. It also shows the driving of ISOLATEn, RETAINn and PWRDOWN for use with state retention cells. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 148: Figure 7-4 Power Down Timing Sequence

    The location of the WICPEND and interrupt OR gates is not important. The clamps are typically inserted by the tools during synthesis. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 149: Figure 7-5 Pmu, Wic, And Cortex-M3 Interconnect

    WICSENSE WICDSACKn WICDSACKn Figure 7-5 PMU, WIC, and Cortex-M3 interconnect The non-clocked circuitry can use the signals out of the WIC to deduce whether a particular interrupt causes the WIC to generate a WAKEUP request, and to provide alternative power reduction methods not supported by the WIC directly. All WIC interrupt related pins are agnostic as to how many, or what combinations of INTISR, NMI, or RXEV are attached as long as the same offset is used throughout the WIC.
  • Page 150 Insert inverters either side of the clamp. • Ensure that the external system masks nTDOEN when the core is powered down. • Clamp nTDOEN to 1 during power down. 7-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 151: Chapter 8 Nested Vectored Interrupt Controller

    This chapter describes the Nested Vectored Interrupt Controller (NVIC). It contains the following sections: • About the NVIC on page 8-2 • NVIC programmer’s model on page 8-3 • Level versus pulse interrupts on page 8-43. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 152: About The Nvic

    All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. Processor exception handling is described in Chapter 5 Exceptions. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 153: Nvic Programmer's Model

    8-12 Irq 0 to 31 Set Enable Register Read/write page 8-13 0xE000E100 0x00000000 Irq 224 to 239 Set Enable Register Read/write page 8-13 0xE000E11C 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 154 8-16 0xE000E300 0x00000000 Irq 224 to 239 Active Bit Register Read-only page 8-16 0xE000E31C 0x00000000 Irq 0 to 3 Priority Register Read/write page 8-17 0xE000E400 0x00000000 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 155 0xE000ED4C 0x00000000 MMFR0: Memory Model Feature register0 Read-only 0xE000ED50 0x00000030 MMFR1: Memory Model Feature register1 Read-only 0xE000ED54 0x00000000 MMFR2: Memory Model Feature register2 Read-only 0xE000ED58 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 156 Reset value depends on the number of interrupts defined. b. Bits [10:8] are reset. The ENDIANESS bit, bit [15], is set at reset by the sampling of BIGEND. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 157: Figure 8-1 Interrupt Controller Type Register Bit Assignments

    Depends on the number of interrupts defined in this processor implementation. Figure 8-1 shows the bit assignments of the Interrupt Controller Type Register. Reserved INTLINESNUM Figure 8-1 Interrupt Controller Type Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 158: Table 8-2 Interrupt Controller Type Register Bit Assignments

    Address 0xE000E008 Access Read/write Reset state 0x00000000 Figure 8-2 shows the bit assignments of the Auxiliary Control Register. Reserved Figure 8-2 Auxiliary Control Register bit assignments Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 159: Table 8-3 Auxiliary Control Register Bit Assignments

    Figure 8-3 shows the bit assignments of the SysTick Control and Status Register. 16 15 Reserved Reserved CLKSOURCE COUNTFLAG TICKINT ENABLE Figure 8-3 SysTick Control and Status Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 160: Table 8-4 Systick Control And Status Register Bit Assignments

    400 clock pulses, 400 must be written into the RELOAD. The register address, access type, and Reset state are: Address 0xE000E014 Access Read/write 8-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 161: Table 8-5 Systick Reload Value Register Bit Assignments

    Reset state Unpredictable Figure 8-5 shows the bit assignments of the SysTick Current Value Register. Reserved CURRENT Figure 8-5 SysTick Current Value Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-11 Non-Confidential Unrestricted Access...

  • Page 162: Table 8-6 Systick Current Value Register Bit Assignments

    Table 8-7 describes the bit assignments of the SysTick Calibration Value Register. Table 8-7 SysTick Calibration Value Register bit assignments Bits Field Function [31] NOREF 1 = the reference clock is not provided. 8-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 163 Clearing an Interrupt Set-Enable Register bit does not affect currently active interrupts. It only prevents new activations. The register address, access type, and Reset state are: Address 0xE000E100-0xE000E11C Access Read/write Reset state 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-13 Non-Confidential Unrestricted Access...

  • Page 164: Table 8-8 Interrupt Set-Enable Register Bit Assignments

    1 = enable interrupt 0 = disable interrupt. Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state. 8-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 165: Table 8-10 Interrupt Set-Pending Register Bit Assignments

    Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-15 Non-Confidential Unrestricted Access...

  • Page 166: Table 8-11 Interrupt Clear-Pending Registers Bit Assignments

    Table 8-12 Active Bit Register bit assignments Bits Field Function [31:0] ACTIVE Interrupt active flags: 1 = interrupt active or pre-empted and stacked 0 = interrupt not active or stacked. 8-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 167: Figure 8-7 Interrupt Priority Registers 0-31 Bit Assignments

    E000E41C Figure 8-7 Interrupt Priority Registers 0-31 bit assignments The lower PRI_n bits can specify subpriorities for priority grouping. See Exception priority on page 5-6. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-17 Non-Confidential Unrestricted Access...

  • Page 168: Table 8-13 Interrupt Priority Registers 0-31 Bit Assignments

    Table 8-14 describes the bit assignments of the CPUID Base Register. Table 8-14 CPUID Base Register bit assignments Bits Field Function [31:24] IMPLEMENTER Implementer code. ARM is 0x41 [23:20] VARIANT Implementation defined variant number. 8-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 169 Number of processor within family: [11:10] b11 = Cortex family [9:8] b00 = version [7:6] b00 = reserved [5:4] b10 = M (v7-M) [3:0] X = family member. Cortex-M3 family is b0011. [3:0] REVISION Implementation defined revision number. Interrupt Control State Register Use the Interrupt Control State Register to: •...

  • Page 170: Table 8-15 Interrupt Control State Register Bit Assignments

    0 = do not set pending SysTick. [25] PENDSTCLR Write-only Clear pending SysTick bit: 1 = clear pending SysTick 0 = do not clear pending SysTick. 8-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 171 The register address, access type, and Reset state are: Address 0xE000ED08 Access Read/write Reset state 0x00000000 Figure 8-10 on page 8-22 shows the bit assignments of the Vector Table Offset Register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-21 Non-Confidential Unrestricted Access...

  • Page 172: Table 8-16 Vector Table Offset Register Bit Assignments

    • execute a system reset • alter the priority grouping position (binary point). 8-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 173: Table 8-17 Application Interrupt And Reset Control Register Bit Assignments

    ENDIANESS is sampled from the BIGEND input port during reset. You cannot change ENDIANESS outside of reset. [14:11] Reserved [10:8] PRIGROUP Interrupt priority grouping field: ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-23 Non-Confidential Unrestricted Access...
  • Page 174 0 = do not reset system. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted. 8-24 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 175: Figure 8-12 System Control Register Bit Assignments

    Figure 8-12 shows the bit assignments of the System Control Register. 4 3 2 1 0 Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Figure 8-12 System Control Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-25 Non-Confidential Unrestricted Access...

  • Page 176: Table 8-18 System Control Register Bit Assignments

    SLEEPDEEP Sleep deep bit: 1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. 0 = not OK to turn off system clock.

  • Page 177: Table 8-19 Configuration Control Register Bit Assignments

    Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register on page 8-35. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-27 Non-Confidential Unrestricted Access...
  • Page 178 The register addresses, access types, and Reset states are: Address 0xE000ED18 0xE000ED1C 0xE000ED20 Access Read/write Reset state 0x00000000 Figure 8-14 on page 8-29 shows the bit assignments of the System Handler Priority Registers. 8-28 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 179: Table 8-20 System Handler Priority Registers Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED24 Access Read/write Reset state 0x00000000 Figure 8-15 on page 8-30 shows the bit assignments of the System Handler and State Control Register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-29 Non-Confidential Unrestricted Access...

  • Page 180: Table 8-21 System Handler Control And State Register Bit Assignments

    Reads as 1 if MemManage is pended. [12] USGFAULTPENDED Read as 1 if usage fault is pended [11] SYSTICKACT Reads as 1 if SysTick is active. 8-30 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 181 SVCall or BusFault handler is started, the bits are not cleared. This enables the push-error or vector-read-error handler to choose to clear them or retry. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-31 Non-Confidential...

  • Page 182: Figure 8-16 Configurable Fault Status Registers Bit Assignments

    The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults. The register address, access type, and Reset state are: Address 0xE000ED28 Access Read/write-one-to-clear Reset state 0x00000000 8-32 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 183: Table 8-22 Memory Manage Fault Status Register Bit Assignments

    SP is not adjusted from failing return and new save is not performed. The MMAR is not written. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-33 Non-Confidential...

  • Page 184: Figure 8-18 Bus Fault Status Register Bit Assignments

    Figure 8-18 shows the bit assignments of the Bus Fault Status Register. 7 6 5 4 3 2 1 0 BFARVALID Reserved STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR Figure 8-18 Bus Fault Status Register bit assignments 8-34 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 185: Table 8-23 Bus Fault Status Register Bit Assignments

    EPSR and instruction • illegal PC load • illegal processor state • instruction decode error • attempt to use a coprocessor instruction • illegal unaligned access. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-35 Non-Confidential Unrestricted Access...

  • Page 186: Table 8-24 Usage Fault Status Register Bit Assignments

    Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP. [7:4] Reserved. NOCP Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. 8-36 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 187: Figure 8-20 Hard Fault Status Register Bit Assignments

    Figure 8-20 shows the bit assignments of the Hard Fault Status Register. 31 30 2 1 0 Reserved FORCED VECTTBL DEBUGEVT Reserved Figure 8-20 Hard Fault Status Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-37 Non-Confidential Unrestricted Access...

  • Page 188: Table 8-25 Hard Fault Status Register Bit Assignments

    If debug and the monitor are both disabled, some of these events are Hard Faults, and the DBGEVT bit is set in the Hard Fault status register, and some are ignored. 8-38 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 189: Table 8-26 Debug Fault Status Register Bit Assignments

    When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-39 Non-Confidential Unrestricted Access...

  • Page 190: Table 8-27 Memory Manage Fault Address Register Bit Assignments

    Flags in the Memory Manage Fault Status Register indicate the cause of the fault. See Memory Manage Fault Status Register on page 8-32. 8-40 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 191: Table 8-28 Bus Fault Address Register Bit Assignments

    When an AFSR bit is written or latched as one, an exception does not occur. If you require an exception, you must use an interrupt. The register address, access type, and Reset state are: Address 0xE000ED3C Access Read/write-clear Reset state 0x00000000 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-41 Non-Confidential Unrestricted Access...

  • Page 192: Table 8-29 Auxiliary Fault Status Register Bit Assignments

    Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. 8-42 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 193: Level Versus Pulse Interrupts

    The processor supports both level and pulse interrupts. A level interrupt is held asserted until it is cleared by the ISR accessing the device. A pulse interrupt is a variant of an edge model. The edge must be sampled on the rising edge of the Cortex-M3 clock, FCLK, instead of being asynchronous.
  • Page 194 Nested Vectored Interrupt Controller 8-44 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 195 Interrupts and updating the MPU on page 9-19 • MPU access permissions on page 9-13 • MPU aborts on page 9-15 • Updating an MPU region on page 9-16. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 196: Chapter 9 Memory Protection Unit

    MemManage fault handler. For more information, see Memory Manage Fault Address Register on page 8-40. You can use the MPU to: • enforce privilege rules • separate processes • enforce access rules. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 197: Mpu Programmer's Model

    Use the MPU Type Register to see how many regions the MPU supports. Read bits [15:8] to determine if an MPU is present. The register address, access type, and Reset state are: Address 0xE000ED90 Access Read-only ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 198: Table 9-2 Mpu Type Register Bit Assignments

    When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 199: Figure 9-2 Mpu Control Register Bit Assignments

    Read/write Reset state 0x00000000 Figure 9-2 shows the bit assignments of the MPU Control Register. Reserved PRIVDEFENA HFNMIENA ENABLE Figure 9-2 MPU Control Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 200: Table 9-3 Mpu Control Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED98 Access Read/write Reset state Unpredictable Figure 9-3 on page 9-7 shows the bit assignments of the MPU Region Number Register. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 201: Table 9-4 Mpu Region Number Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000ED9C Access Read/write Reset state Unpredictable Figure 9-4 on page 9-8 shows the bit assignments of the MPU Region Base Address Register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 202: Table 9-5 Mpu Region Base Address Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE000EDA0 Access Read/write Reset state Unpredictable Figure 9-5 on page 9-9 shows the bit assignments of the MPU Region Attribute and Size Register. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 203: Table 9-6 Mpu Region Attribute And Size Register Bit Assignments

    [23:22] Reserved. [21:19] Type extension field. [18] Shareable bit: 1 = shareable 0 = not shareable. [17] Cacheable bit: 1 = cacheable 0 = not cacheable. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 204: Table 9-7 Mpu Protection Region Size Field

    Table 9-7 MPU protection region size field Region Size b00000 Reserved b00001 Reserved b00010 Reserved b00011 Reserved b00100 b00101 b00110 128B b00111 256B b01000 512B b01001 b01010 b01011 b01100 b01101 16KB 9-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 205 The aliases access the registers in exactly the same way, and they exist to enable the use of sequential writes (STM) to update between one and four regions. This is used when disable/change/enable is not required. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-11 Non-Confidential Unrestricted Access...
  • Page 206 512KB. The bottom 64KB of the 512KB region is disabled so that the attributes from the 64KB apply. This is achieved by setting SRD for the 512KB region to b00000001. 9-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 207: Mpu Access Permissions

    Cached memory BB = outer policy. Normal AA = inner policy. Note In Table 9-8, S is the S bit [2] from the MPU Region Attributes and Size Register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-13 Non-Confidential Unrestricted Access...

  • Page 208: Table 9-9 Cache Policy For Memory Attribute Encoding

    Read only Read only Privileged/user read only Table 9-11 describes the XN encoding. Table 9-11 XN encoding Description All instruction fetches enabled Instruction fetches disabled 9-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 209: Mpu Aborts

    Memory Protection Unit MPU aborts For information about MPU aborts, see Memory Manage Fault Address Register on page 8-40. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-15 Non-Confidential Unrestricted Access...

  • Page 210: Updating An Mpu Region

    STR R1,[R0,#0]; region number BIC R2,R2, #1; disable STRH R2,[R0,#8]; size and enable STR R4,[R0,#4]; address STRH R3,[R0,#10]; attributes ORR R2,#1; enable STRH R2,[R0,#8]; size and enable 9-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 211 An STM can optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one MOV R0,#NVIC_BASE ADD R0,#MPU_REG_CTRL ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-17 Non-Confidential Unrestricted Access...
  • Page 212 Memory Protection Unit STM R0,{R1-R2}; address, region number, size For information about interrupts and updating the MPU, see Interrupts and updating the MPU on page 9-19. 9-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 213: Interrupts And Updating The Mpu

    If these are the only two places, and the context switcher is only updating user regions, then disable is not required because the context switcher is already a critical region and the boot code runs with interrupts disabled. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-19 Non-Confidential Unrestricted Access...
  • Page 214 Memory Protection Unit 9-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 215 • Core debug registers on page 10-3 • Core debug access example on page 10-12 • Using application registers in core debug on page 10-13. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-1 Non-Confidential Unrestricted Access...

  • Page 216: Chapter 10 Core Debug

    S_HALT bit of the Debug Halting Control and Status Register. 10.1.2 Exiting core debug The core can exit Halting debug by clearing the C_DEBUGEN bit in the Debug Halting and Status Register. 10-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 217: Core Debug Registers

    The DHCSR is only reset from a system reset, including power on. Bit 16 of DHCSR is Unpredictable on reset. Figure 10-1 on page 10-4 shows the bit assignments in the register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-3 Non-Confidential Unrestricted Access...

  • Page 218: Table 10-2 Debug Halting Control And Status Register

    This determines if the core is stalled on a load/store or fetch. [23:20] Reserved, RAZ. [19] Read S_LOCKUP Reads as one if the core is running (not halted) and a lockup condition is present. 10-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 219 The core must write a 1 to it when writing C_HALT to halt itself. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-5 Non-Confidential...

  • Page 220: Figure 10-2 Debug Core Register Selector Register Bit Assignments

    0xE000EDF4 Figure 10-2 shows the bit assignments in the register. Reserved Reserved REGSEL REGWnR Figure 10-2 Debug Core Register Selector Register bit assignments 10-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 221: Table 10-3 Debug Core Register Selector Register

    All bits can be written, but some combinations cause a fault when execution is resumed. • IT might be written and behaves as though in an IT block. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-7 Non-Confidential Unrestricted Access...
  • Page 222 Debug monitor control. The DEMCR: • is a 32-bit read/write register • has address 0xE000EDFC. Figure 10-2 on page 10-6 shows the bit assignments in the register. 10-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 223: Table 10-4 Debug Exception And Monitor Control Register

    This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-9 Non-Confidential Unrestricted Access...
  • Page 224 CAR register. Read/write Debug trap on Memory Management faults. VC_MMERR [3:1] Reserved, SBZP Read/write Reset Vector Catch. Halt running system if Core reset occurs. VC_CORERESET 10-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 225 If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-11 Non-Confidential Unrestricted Access...

  • Page 226: Core Debug Access Example

    Write the value that you want to be written to the Debug Core Register Data Register. Write the register number that you want to write to into the Debug Core Register Selector Register. 10-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 227: Using Application Registers In Core Debug

    ISRPENDING VECTPENDING. Vector Table Offset To find vector table Application Interrupt/Reset Control VECTCLRACTIVE ENDIANESS Configuration Control DIV_0_TRP UNALIGN_TRP. System Handler Control and State ACTIVE PENDED ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-13 Non-Confidential Unrestricted Access...
  • Page 228 Core Debug 10-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 229 System debug programmer’s model on page 11-5 • FPB on page 11-6 • DWT on page 11-13 • ITM on page 11-30 • AHB-AP on page 11-39. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-1 Non-Confidential Unrestricted Access...

  • Page 230: About System Debug

    Note • For a description of the Core debug, see Chapter 10 Core Debug. 11-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 231: System Debug Access

    — Trace Port Interface Unit (TPIU). This component acts as a bridge between the Cortex-M3 trace data (from the ITM, and ETM if present) and an off-chip Trace Port Analyzer. See Chapter 17 Trace Port Interface Unit for more information.

  • Page 232: Figure 11-1 System Debug Access Block Diagram

    External Private Peripheral Bus (PPB) Bridge SW/SWJ-DP AHB-AP NVIC Trace port TPIU Internal Private Peripheral Bus (PPB) ROM table Figure 11-1 System debug access block diagram 11-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 233: System Debug Programmer's Model

    For a description of the SWJ-DP and SW-DP registers see Chapter 13 Debug Port. • For a description of the TPIU, see Chapter 17 Trace Port Interface Unit. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-5 Non-Confidential Unrestricted Access...

  • Page 234: Fpb

    Remapping to the bit-band alias directly accesses the alias address, and does not remap to the bit-band region. 11.4.1 FPB programmer’s model Table 11-1 on page 11-7 lists the flash patch registers. 11-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 235: Table 11-1 Fpb Register Summary

    PID0 Read-only 0xE0002FE0 Value 0x03 PID1 Read-only 0xE0002FE4 Value 0xB0 PID2 Read-only Value 0xE0002FE8 0x2B PID3 Read-only Value 0xE0002FEC 0x00 CID0 Read-only Value 0xE0002FF0 0x0D ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-7 Non-Confidential Unrestricted Access...

  • Page 236: Table 11-2 Flash Patch Control Register Bit Assignments

    Number of literal slots field. This read only field contains either b0000 to indicate there are no literal slots or b0010 to indicate that there are two literal slots. 11-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...
  • Page 237 A comparison match remaps to: {3’b001, REMAP, COMP[2:0], HADDR[1:0]} where: • 3’b001 hardwires the remapped access to system space • REMAP is the 24-bit, 8-word aligned remap address ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-9 Non-Confidential Unrestricted Access...

  • Page 238: Table 11-3 Comp Mapping

    Figure 11-3 shows the bit assignments of the Flash Patch Remap Register. 29 28 REMAP Reserved Reserved Figure 11-3 Flash Patch Remap Register bit assignments 11-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 239: Table 11-4 Flash Patch Remap Register Bit Assignments

    REPLACE ENABLE Figure 11-4 Flash Patch Comparator Registers bit assignments Table 11-5 on page 11-12 describes the bit assignments of the Flash Patch Comparator Registers. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-11 Non-Confidential Unrestricted Access...

  • Page 240: Table 11-5 Flash Patch Comparator Registers Bit Assignments

    0 = Flash Patch Comparator Register n compare and remap disabled. The ENABLE bit of FP_CTRL must also be set to enable comparisons. Reset clears the ENABLE bit. 11-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 241: Dwt

    You can configure any of the DWT registers to be present or not present. Any register that is configured as not present reads as zero. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-13 Non-Confidential Unrestricted Access...

  • Page 242: Table 11-6 Dwt Register Summary

    0xE0001054 DWT_FUNCTION3 Read/write See DWT Function Registers 0-3 on page 11-25 0xE0001058 0x00000000 PID4 Read-only Value 0xE0001FD0 0x04 0x04 PID5 Read-only Value 0xE0001FD4 0x00 0x00 11-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 243 0x1F000000 0x00000000 if DWT is not present. Figure 11-5 on page 11-16 shows the bit assignments of the DWT Control Register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-15 Non-Confidential Unrestricted Access...

  • Page 244: Table 11-7 Dwt Control Register Bit Assignments

    0 = Cycle count events disabled. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit. 11-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 245 [16] EXCTRCENA Enables Interrupt event tracing: 1 = interrupt event trace enabled 0 = interrupt event trace disabled. Reset clears the EXCEVTENA bit. [15:13] Reserved ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-17 Non-Confidential Unrestricted Access...
  • Page 246 Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0. 11-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 247: Table 11-8 Dwt Current Pc Sampler Cycle Count Register Bit Assignments

    When CYCEVTENA is set (and PCSAMPLENA is clear), an event is emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-19 Non-Confidential Unrestricted Access...

  • Page 248: Table 11-9 Dwt Cpi Count Register Bit Assignments

    Use the DWT Exception Overhead Count Register to count the total cycles spent in interrupt processing. The register address, access type, and Reset state are: Address 0xE000100C 11-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 249: Table 11-10 Dwt Exception Overhead Count Register Bit Assignments

    Read-write Reset state Figure 11-8 shows the bit assignments of the DTW Sleep Count Register. Reserved SLEEPCNT Figure 11-8 DWT Sleep Count Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-21 Non-Confidential Unrestricted Access...

  • Page 250: Table 11-11 Dwt Sleep Count Register Bit Assignments

    Read/write Reset state Figure 11-9 describes the bit assignments of the DWT LSU Count Register. Reserved LSUCNT Figure 11-9 DWT LSU Count Register bit assignments 11-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 251: Table 11-12 Dwt Lsu Count Register Bit Assignments

    Table 11-13 DWT Fold Count Register bit assignments Bits Field Function [31:8] Reserved. [7:0] FOLDCNT This counts the total number folded instructions. This counter initializes to 0 when enabled. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-23 Non-Confidential Unrestricted Access...

  • Page 252: Table 11-14 Dwt Program Counter Sample Register Bit Assignments

    DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT). DWT_COMP1 can also compare against data values so that data matching can be performed (DATAVMATCH). 11-24 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 253: Table 11-16 Dwt Mask Registers 0-3 Bit Assignments

    CYCMATCH. This function is only available for comparator 0 (DWT_COMP0). • Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (DWT_COMP1). ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-25 Non-Confidential Unrestricted Access...

  • Page 254: Table 11-17 Bit Functions Of Dwt Function Registers 0-3

    Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. [15:12] DATAVADDR0 Identity of a linked address comparator for data value matching when DATAVMATCH == 11-26 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 255 EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. Reserved. [3:0] FUNCTION See Table 11-18 on page 11-28 for FUNCTION settings. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-27 Non-Confidential Unrestricted Access...

  • Page 256: Table 11-18 Settings For Dwt Function Registers

    EMITRANGE = 1, sample Daddr [15:0] + data for write transfers Note • If the ETM is not fitted, then ETM trigger is not possible. 11-28 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 257 • PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-29 Non-Confidential Unrestricted Access...

  • Page 258: Itm

    Hardware trace. The DWT generates these packets, and the ITM emits them. • Time stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M3 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter. 11.6.1...
  • Page 259 Stimulus Registers and Trace Enable Registers can be written, and only when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the ITM registers are discarded. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-31 Non-Confidential Unrestricted Access...

  • Page 260: Table 11-20 Itm Trace Enable Register Bit Assignments

    The polled FIFO interface does not provide an atomic read-modify-write, so you must use the Cortex-M3 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads. The following polled code guarantees stimulus is not lost by polled access to the ITM: ;...

  • Page 261: Table 11-21 Itm Trace Privilege Register Bit Assignments

    Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0] bit [1] = stimulus ports [15:8] bit [2] = stimulus ports [23:16] bit [3] = stimulus ports [31:24]. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-33 Non-Confidential Unrestricted Access...

  • Page 262: Table 11-22 Itm Trace Control Register Bit Assignments

    Table 11-22 ITM Trace Control Register bit assignments Bits Field Function [31:24] 0b00000000. [23] BUSY Set when ITM events present and being drained [22:16] ATBID ATB ID for CoreSight system. [15:10] 0b000000. 11-34 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 263: Figure 11-15 Itm Integration Write Register Bit Assignments

    Use this register to determine the behavior of the ATVALIDM bit. Figure 11-15 shows the ITM Integration Write Register bit assignments. Reserved ATVALIDM Figure 11-15 ITM Integration Write Register bit assignments ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-35 Non-Confidential Unrestricted Access...

  • Page 264: Table 11-23 Itm Integration Write Register Bit Assignments

    Bits Field Function [31:1] Reserved ATREADYM Value on ATREADYM ITM Integration Mode Control Register Use this register to enable write accesses to the Control Register. 11-36 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 265: Table 11-25 Itm Integration Mode Control Register Bit Assignments

    ITM Lock Status Register Use this register to enable write accesses to the Control Register. Figure 11-18 on page 11-38 shows the ITM Lock Status Register bit assignments. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-37 Non-Confidential Unrestricted Access...

  • Page 266: Table 11-27 Itm Lock Status Register Bit Assignments

    You cannot implement 8-bit lock accesses. Access Write access to component is blocked. All writes are ignored, reads are permitted. Present Indicates that a lock mechanism exists for this component. 11-38 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 267: Ahb-Ap

    11.7 AHB-AP AHB-AP is an optional debug access port into the Cortex-M3 system, and provides access to all memory and registers in the system, including processor registers through the NVIC. System access is independent of the processor status. Either SW-DP or SWJ-DP accesses AHB-AP.

  • Page 268: Table 11-28 Ahb-Ap Register Summary

    Use this register to configure and control transfers through the AHB interface. Figure 11-19 shows the bit assignments of the AHB-AP Control and Status Word Register. 11-40 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 269: Table 11-29 Ahb-Ap Control And Status Word Register Bit Assignments

    Indicates the status of the DAPEN port. If DbgStatus is LOW, no AHB transfers carried out. 1 = AHB transfers permitted. 0 = AHB transfers not permitted. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-41 Non-Confidential Unrestricted Access...

  • Page 270: Table 11-30 Ahb-Ap Transfer Address Register Bit Assignments

    Table 11-30 describes the bit assignments of the AHB-AP Transfer Address Register. Table 11-30 AHB-AP Transfer Address Register bit assignments Bits Field Function [31:0] ADDRESS Current transfer address. No reset value. 11-42 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 271: Table 11-31 Ahb-Ap Data Read/Write Register Bit Assignments

    No reset value. AHB-AP Debug ROM Address Register This register specifies the base address of the debug interface. It is read-only. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-43 Non-Confidential Unrestricted Access...

  • Page 272: Table 11-33 Ahb-Ap Debug Rom Address Register Bit Assignments

    This field is zero for the first implementation of an AP design, and is updated for each major revision of the design. [27:24] JEP-106 continuation code For an ARM-designed AP, this field has value 0b0100, [23:17] JEP-106 identity code For an ARM-designed AP, this field has value 0b0111011,...
  • Page 273 • Bit-band accesses on page 12-13 • Write buffer on page 12-14 • Memory attributes on page 12-15 • AHB timing characteristics on page 12-16. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-1 Non-Confidential Unrestricted Access...

  • Page 274: Chapter 12 Bus Interface

    The processor contains an internal PPB for accesses to the Nested Vectored Interrupt Controller (NVIC), Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Flash Patch and Breakpoint (FPB), and Memory Protection Unit (MPU). 12-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 275: Amba 3 Compliance

    Note Logic can be implemented external to Cortex-M3 if necessary to achieve total compliance, but this is only required if peripherals require the control information to be maintained through a waited transfer. One way of implementing this is to mask the control information, such as HTRANS, while HREADY is low.

  • Page 276: Icode Bus Interface

    HPROTI[3:2] = 2'b10, and as allocate and non-shareable, MEMATTRI = 2'b01. These attributes are hard wired. If an MPU is fitted, the MPU region attributes are ignored for the ICode bus. 12-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 277 For more information about the branch status signal, see Chapter 15 Embedded Trace Macrocell Interface. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-5 Non-Confidential Unrestricted Access...

  • Page 278: Dcode Bus Interface

    The DCode bus supports exclusive accesses. This is carried out using two sideband signals, EXREQD and EXRESPD. For more information, see DCode interface on page A-9. For more information about semaphores and the local exclusive monitor see the ARM Architecture Memory Model chapter in the ARMv7M ARM Architecture Reference Manual.

  • Page 279: System Interface

    The System bus supports exclusive accesses. This is carried out using two sideband signals, EXREQS and EXRESPS. For more information, see System bus interface on page A-10. For more information about semaphores and the local exclusive monitor see the ARM Architecture Memory Model chapter in the ARMv7M ARM Architecture Reference Manual.
  • Page 280 System bus are not possible. Note Instruction fetch requests to the ICode bus are not registered. Performance critical code must run from the ICode interface. 12-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 281: Unifying The Code Buses

    Note DNOTITRANS is a static input that must be tied high to enforce this behavior. The external ICode/DCode bus multiplexer can be integrated into a Cortex-M3 system as Figure 12-1 shows. AHBI...

  • Page 282: External Private Peripheral Interface

    Unaligned accesses to this bus are architecturally Unpredictable and are not supported. The processor drives out the original HADDR[1:0] request from the core and does not convert the request into multiple aligned accesses. 12-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 283: Access Alignment

    Instead, they are treated as a halfword or byte access to the bit-band alias region. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-11 Non-Confidential Unrestricted Access...

  • Page 284: Unaligned Accesses That Cross Regions

    (the first byte of the bit-band alias). Unaligned loads that match against a literal comparator in the FPB are not remapped. FPB only remaps aligned addresses. 12-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 285: 12.10 Bit-Band Accesses

    For more information about bit-banding, see Bit-banding on page 4-5. Note • The Cortex-M3 core does not stall during bit-band operations unless it attempts to access the System bus while the bit-band operation is being carried out. ARM DDI 0337G Copyright ©...

  • Page 286: 12.11 Write Buffer

    DMB/DSB is waiting for the write buffer to drain, the opcode after the DMB/DSB is returned to on the completion of the interrupt. This is because interrupt processing is a memory barrier operation. 12-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 287: 12.12 Memory Attributes

    Device L1 cacheable, L2 not cacheable Invalid Invalid Cache WT, allocate on read Cache WB, allocate on read and write Cache WB, allocate on read ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 12-15 Non-Confidential Unrestricted Access...

  • Page 288: 12.13 Ahb Timing Characteristics

    AHB interfaces unregistered. Because of this, the Cortex-M3 AHB outputs are valid approximately 50% into the cycle, and the AHB inputs have a setup requirement of approximately 50% of the clock period.

  • Page 289: Chapter 13 Debug Port

    Chapter 13 Debug Port This chapter describes the processor Debug Port (DP). It contains: • About the DP on page 13-2. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 13-1 Non-Confidential Unrestricted Access...

  • Page 290: About The Dp

    The SWJ-DP is designed to permit pin sharing of JTAG-TDO and JTAG-TDI when they are not being used for JTAG debug access. When used together with a Cortex-M3 TPIU, there are different options for the connection of Serial Wire Output (SWO), see Serial wire output connection on page 17-21.
  • Page 291 • ETM resources on page 14-8 • Trace output on page 14-11 • ETM architecture on page 14-12 • ETM programmer’s model on page 14-16. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-1 Non-Confidential Unrestricted Access...

  • Page 292: Chapter 14 Embedded Trace Macrocell

    Figure 14-1 on page 14-3 shows a block diagram of the ETM, and shows how the ETM interfaces to the Trace Port Interface Unit (TPIU). 14-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 293: Figure 14-1 Etm Block Diagram

    Trace port signals. See Table 14-2 on page 14-4. • Other signals. See Table 14-4 on page 14-5. • Clocks and resets. See Table 14-5 on page 14-6. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-3 Non-Confidential Unrestricted Access...

  • Page 294: Table 14-1 Etm Core Interface Inputs And Outputs

    PC value (set) or data address (clear). Table 14-2 Miscellaneous configuration inputs Name Description Direction Clock domain NIDEN Non invasive debug enable Input FCLK EXTIN[1:0] External input resource Input FCLK 14-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 295: Table 14-3 Trace Port Signals

    Indicates that the ETM is powered up Output FCLK ETMTRIGOUT Trigger occurred status signal Output HCLK ETMDBGRQ Debug request to core Output FCLK ETMEN ETM traceport enabled Output FCLK ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-5 Non-Confidential Unrestricted Access...

  • Page 296: Table 14-5 Clocks And Resets

    Table 14-5 Clocks and resets Name Description Direction FCLK Clock for ETM logic which must be connected to the same FCLK as Cortex-M3. Input PORRESETn Power on reset for the HCLK domain. Must not be the same as core HCLK reset Input (SYSRESETn).

  • Page 297: Data Tracing

    TPIU, where they are combined and usually output over the trace port. DWT is able to provide either focused data trace, or global data trace, subject to FIFO overflow issues. The TPIU is optimized for the requirements of a single core Cortex-M3 system.

  • Page 298: Etm Resources

    Embedded ICE comparators External inputs External outputs Extended external inputs Extended external input selectors FIFOFULL FIFOFULL level setting Branch broadcasting ASIC Control Register Data suppression 14-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 299 ETM as Embedded In Circuit Emulator (ICE) comparator inputs. A single DWT resource can trigger an ETM event and also generate instrumentation trace directly from the same event. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-9 Non-Confidential Unrestricted Access...
  • Page 300 Although stalling the core in a typical application is unlikely to be acceptable, it provides a mechanism for enabling 100% trace that could be compared with the partial trace obtained for a non-stalled run. 14-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 301: Trace Output

    ETM FIFO. However, with an 8-bit ATB port the FIFO always drains, which makes AFVALID unnecessary. The Cortex-M3 system is equipped with an optimized TPIU that is designed for use with the ETM and ITM. This TPIU does not support additional trace sources. However, you can add additional trace sources if the TPIU has been replaced with a more complex version, and more trace infrastructure.

  • Page 302: Etm Architecture

    Embedded Trace Macrocell 14.5 ETM architecture The ETM is an instruction only ETM that implements ARM ETM architecture v3.4. It is based on the ARM ETM Architecture Specification. For full details, see the ARM Embedded Trace Macrocell Architecture Specification. All 32-bit Thumb instructions are traced as a single instruction. Instructions following an IT instruction are traced as normal conditional instructions.

  • Page 303: Table 14-8 Exception Tracing Mapping

    SysTick 2 bytes exception Reserved 2 bytes exception Reset 2 bytes exception Reserved 2 bytes exception HardFault 2 bytes exception Reserved 2 bytes exception BusFault ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-13 Non-Confidential Unrestricted Access...

  • Page 304: Figure 14-3 Exception Encoding For Branch Packet

    Address byte 4 Addr[31:28] (optional) Exception information T2EE Canc Excp[3:0] Byte 0 Exception information Excp[8:4] Byte 1 (optional) Figure 14-3 Exception encoding for branch packet 14-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 305 When turning off trace immediately before entry to an exception handler, the ETM remains enabled until the exception is taken. This enables it to trace the branch address, exception type and resume information. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-15 Non-Confidential Unrestricted Access...

  • Page 306: Etm Programmer's Model

    Serial Wire Debug Port/JTAG Debug Port (SW-DP/JTAG-DP). 14.6.2 List of ETM registers The ETM registers are listed in Table 14-9. For full details, see the ARM Embedded Trace Macrocell Architecture Specification. Table 14-9 ETM registers Name...
  • Page 307 0xE0041040 0xE004113C Counters 0xE0041140 0xE004157C Sequencer 0xE0041180 0xE0041194 0xE0041198 External Outputs 0xE00411A0 0xE00411AC CID Comparators 0xE00411B0 0xE00411BC Implementation specific All RAZ. Ignore writes. 0xE00411C0 0xE00411DC ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-17 Non-Confidential Unrestricted Access...
  • Page 308 Read/write 0xE0041FA0 Implements the 4-bit claim tag. 0xE0041FA4 Lock Access Write only Implemented as normal. 0xE0041FB0 0xE0041FB4 Lock Status Read only Implemented as normal. 0xE0041Fb4 14-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 309 14.6.3 Description of ETM registers An additional description of some of the ETM registers is given in the following sections. See the ARM Embedded Trace Macrocell Architecture Specification for more information. ETM Control Register The ETM Control Register controls general operation of the ETM, such as whether tracing is enabled.
  • Page 310 The System Configuration Register shows the ETM features supported by the ASIC. Reset value: 0x00020D09 Bits [11:10] are implemented as normal. Bits [9], [2:0] are fixed as 4’b0001. 14-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 311 In Circuit Emulator (ICE) inputs • four embedded ICE inputs • no data comparisons supported • all registers are readable • no extended external input supported. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-21 Non-Confidential Unrestricted Access...

  • Page 312: Table 14-10 Boolean Function Encoding For Events

    A AND B b011 NOT(A) AND B b100 NOT(A) AND NOT (B) b101 A OR B b110 NOT (A) OR B b111 NOT (A) OR NOT (B) 14-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 313: Table 14-11 Resource Identification Encoding

    DBGACK Core Compulsory. Table 14-13 Trigger output connections Trigger bit Source signal Source device Comments User defined User defined ETMEXTIN[1] Compulsory if ETM is present. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-23 Non-Confidential Unrestricted Access...
  • Page 314 There is no connection from ETMDBGREQ of the ETM to the CTI. If required, this signal must be ORed with an external debug request input, and trigger bit [0] from the CTI. 14-24 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 315: Chapter 15 Embedded Trace Macrocell Interface

    • About the ETM interface on page 15-2 • CPU ETM interface port descriptions on page 15-3 • Branch status interface on page 15-6. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-1 Non-Confidential Unrestricted Access...

  • Page 316: About The Etm Interface

    About the ETM interface The ETM interface enables simple connection of an ETM to the processor. It provides a channel for instruction trace to the ETM. 15-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 317: Cpu Etm Interface Port Descriptions

    Entry/Return is asserted in the first cycle of the new interrupt context. Exit occurs without ETMIVALID. ETMINTNUM[8:0] Output ETMINTSTAT Interrupt number. Marks the interrupt number of the current execution context. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-3 Non-Confidential Unrestricted Access...
  • Page 318 Current opcode in execute has been cancelled. Opcodes that are interrupted restart or continue on return to this execution context. These include: LDR/STR LDRD/STRD LDM/STM U/SMULL U/SDIV CPSID 15-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 319 Output trigger from DWT. One bit for each of the four DWT comparators. ETMTRIGINOTD[3:0] Output No qualifier Output indicates if the ETM is triggered on an instruction or data match. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-5 Non-Confidential Unrestricted Access...

  • Page 320: Branch Status Interface

    This means that when ever a branch immediate enters the decode stage the branch target address is issued on the AHB. 15-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 321: Table 15-3 Branches And Stages Evaluated By The Processor

    MOV PC 32 bits Execute If LR is not the source register or if LR is being written during decode and LR is the source register. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-7 Non-Confidential Unrestricted Access...

  • Page 322: Figure 15-1 Conditional Branch Backwards Not Taken

    The branch target is a halfword unaligned 16-bit opcode. HCLK ETMIVALID ETMCCFAIL ETMIA BRCHSTAT 0001 0000 HTRANSI NONSEQ HADDRI Fetch ahead of Figure 15-1 Conditional branch backwards not taken 15-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 323: Figure 15-2 Conditional Branch Backwards Taken

    Figure 15-3 Conditional branch forwards not taken HCLK ETMIVALID ETMCCFAIL ETMIA BRCHSTAT 0010 1000 0000 HTRANSI NONSEQ NONSEQ NONSEQ IDLE IDLE IDLE HADDRI Figure 15-4 Conditional branch forwards taken ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-9 Non-Confidential Unrestricted Access...

  • Page 324: Figure 15-5 Unconditional Branch Without Pipeline Stalls

    The branch occurs in the execute phase of the opcode. The branch target is an aligned and unaligned 32-bit ALU opcode. 15-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 325: Table 15-4 Example Of An Opcode Sequence

    LDR r3,[r4] 0x1024 ADD r2,#3 0x1026 CMP r3,r2 0x1028 BEQ = Target1 0x1040 CMP r1,r2 // folded 0x1042 ITE EQ // skipped 0x1044 LDR EQ r3,[r4,r1] ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-11 Non-Confidential Unrestricted Access...
  • Page 326 // not taken 0x0FC8 BX r5 Figure 15-9 on page 15-13 shows the timing sequence for the example opcode sequence in Table 15-4 on page 15-11. 15-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 327: Figure 15-9 Example Of An Opcode Sequence

    ADD CMP BEQ ADD NOP BX BEQ BX Execute op ADD CMP BEQ ADD NOP BX BEQ BX Figure 15-9 Example of an opcode sequence ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-13 Non-Confidential Unrestricted Access...
  • Page 328 Embedded Trace Macrocell Interface 15-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 329: Chapter 16 Ahb Trace Macrocell Interface

    It contains the following sections: • About the AHB trace macrocell interface on page 16-2 • CPU AHB trace macrocell interface port descriptions on page 16-3. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 16-1 Non-Confidential Unrestricted Access...

  • Page 330: About The Ahb Trace Macrocell Interface

    To use the HTM interface, the trace level must be set to level 3 before implementation. TRCENA must also be set to 1 before you enable the HTM to enable the HTM port to supply trace data. 16-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 331: Cpu Ahb Trace Macrocell Interface Port Descriptions

    The transfer response status. OKAY or ERROR. HTMDHADDR[31:0] Output 32-bit address. HTMDHTRANS[1:0] Output Output indicates the type of the current data transfer. Can be IDLE, NONSEQUENTIAL, OR SEQUENTIAL. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 16-3 Non-Confidential Unrestricted Access...
  • Page 332 AHB Trace Macrocell Interface 16-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 333 This chapter describes the Trace Port Interface Unit (TPIU). It contains the following sections: • About the TPIU on page 17-2 • TPIU registers on page 17-8 • Serial wire output connection on page 17-21. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-1...

  • Page 334: Chapter 17 Trace Port Interface Unit

    If the implementation requires no trace support then the TPIU might not be present. Note If your Cortex-M3 system uses the optional ETM component, you must use the TPIU configuration that supports both ITM and ETM debug trace. For a full description of the ETM, see Chapter 14 Embedded Trace Macrocell.

  • Page 335: Figure 17-1 Tpiu Block Diagram (Non-Etm Version)

    TRACECLKIN Domain CLK Domain TRACECLKIN TRACECLK Asynchronous Trace Out Formatter Interface FIFO (serializer) TRACEDATA Slave [3:0] Port TRACESWO Slave Interface Port Figure 17-1 TPIU block diagram (non-ETM version) ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-3...

  • Page 336: Figure 17-2 Tpiu Block Diagram (Etm Version)

    The formatter inserts source ID signals into the data packet stream so that trace data can be re-associated with its trace source. The formatter is always active when the TRACEPORT mode is active. 17-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 337: Table 17-1 Trace Out Port Signals

    Power on Reset, and must be synchronized to TRACECLKIN. TRACECLK Output TRACEDATA changes on both edges of TRACECLK. TRACEDATA[3:0] Output Output data for clocked modes. TRACESWO Output Output data for asynchronous modes. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-5...

  • Page 338: Table 17-2 Atb Port Signals

    Input Global trace synchronization trigger. Inserts synchronization packets into the formatted data stream. Only used when the formatter is active. This signal must be connected to the DSYNC output from Cortex-M3. TRIGGER Input Causes a trigger packet to be inserted into the trace stream when the formatter is active.

  • Page 339: Table 17-4 Apb Interface

    Table 17-4 APB interface Name Type Description PSEL Input Peripheral select PWRITE Input Peripheral write control PENABLE Input Peripheral transfer enable PADDR[11:2] Input Peripheral address PWDATA[31:0] Write data PRDATA[31:0] Read data ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-7...

  • Page 340: Tpiu Registers

    Integration register : FIFO data 1 Read only page 17-18 0xE0040EFC 0x--000000 Claim tag set register Read/write page 17-20 0xE0040FA0 Claim tag clear register Read/write page 17-19 0xE0040FA4 17-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...
  • Page 341 TPA cannot capture. The value on MAXPORTSIZE causes bits within the Supported Port Size register that represent wider widths to be clear, that is, unsupported. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-9...

  • Page 342: Table 17-6 Async Clock Prescaler Register Bit Assignments

    Table 17-6 describes the bit assignments of the Async Clock Prescaler Register. Table 17-6 Async Clock Prescaler Register bit assignments Bits Field Function [31:13] Reserved. RAZ/SBZP. [12:0] PRESCALER Divisor for TRACECLKIN is Prescaler + 1. 17-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 343: Table 17-7 Selected Pin Protocol Register Bit Assignments

    Use the Formatter and Flush Status Register to read the status of TPIU formatter. The register address, access type, and Reset state are: Address 0xE0040300 Access Read only Reset state 0x08 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-11...

  • Page 344: Table 17-8 Formatter And Flush Status Register Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0040304 Access Read/write Reset state 0x102 Figure 17-7 on page 17-13 shows the bit assignments of the Formatter and Flush Control Register. 17-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 345: Table 17-9 Formatter And Flush Control Register Bit Assignments

    Indicate a trigger on TRIGIN being asserted. Reserved. FOnMan Manually generate a flush of the system. FOnTrig Generate flush using Trigger event. FOnFlln Generate flush using the FLUSHIN interface. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-13...
  • Page 346 This means that there is no synchronization counter in the TPIU. The register address, access type, and Reset state are: Address 0xE0040308 Access Read only Reset state 0x00 17-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 347: Table 17-10 Integration Test Register-Itatbctr2 Bit Assignments

    Use the Integration Test Registers to perform topology detection of the TPIU with other devices in a Cortex-M3 system. These registers enable direct control of outputs and the ability to read the value of inputs. The processor provides two Integration Test Registers: •...

  • Page 348: Table 17-11 Integration Test Register-Itatbctr0 Bit Assignments

    Reset state Figure 17-10 shows the bit assignments of the Integration Mode Control Register. FIFO test mode Integration test mode Figure 17-10 Integration Mode Control Register bit assignments 17-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 349: Table 17-12 Integration Mode Control Register Bit Assignments

    Reserved TRIGGER input value Enables the TRIGGER input Integration Register : FIFO data 0 The register address, access type, and Reset state are: Address 0xE0040EEC Access Read only ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-17...

  • Page 350: Table 17-14 Integration Register : Fifo Data 0 Bit Assignments

    The register address, access type, and Reset state are: Address 0xE0040EFC Access Read only Reset state Figure 17-13 on page 17-19 shows the bit assignments of the Integration register : FIFO data 1. 17-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 351: Table 17-15 Integration Register : Fifo Data 1 Bit Assignments

    Reset state This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-19...
  • Page 352 The register address, access type, and Reset state are: Address 0xE0040FC8 Access Read only Reset state 0xCA0/0xCA1 This register returns: • if there is no ETM present. 0xCA0 • 0xCA1 if there is no ETM present. 17-20 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 353: Serial Wire Output Connection

    Trace Port Interface Unit 17.3 Serial wire output connection The Cortex-M3 TPIU provides a serial wire output mode that requires a single external pin. There are three options available to connect this pin: • A dedicated pin can be used for TRACESWO •...

  • Page 354: Figure 17-15 Swo Shared With Traceport

    To implement this option, the JTAGNSW output from SWJ-DP is used to control the multiplexor. Figure 17-16 shows the SWO shared with JTAG-TDO option. CortexM3Integration TRACEDATA[3:0] TRACEDATA[3:0] SWJ-DP CM3TPIU TRACESWO TDO/SWV JTAGTDO JTAGNSW Figure 17-16 SWO shared with JTAG-TDO 17-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G...

  • Page 355: Chapter 18 Instruction Timing

    This chapter describes the instruction timings of the processor. It contains the following sections: • About instruction timing on page 18-2 • Processor instruction timings on page 18-3 • Load-store timings on page 18-7. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 18-1 Non-Confidential Unrestricted Access...

  • Page 356: About Instruction Timing

    Every instruction must be fetched and every load/store must go out to the system. These factors are described along with intended system design, and the implications for timing. 18-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 357: Processor Instruction Timings

    ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, 1 (+P if PC is destination) with 3 register CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}. No PKxxx instructions. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 18-3 Non-Confidential Unrestricted Access...
  • Page 358 Extended32 NOP and YIELD (hinted NOP). No MRS (1), MSR (1), or SUBS (PC return link). 18-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 359 ISB takes one cycle (acts as branch). DMB and DSB take one cycle unless data is pending in the write buffer or LSU. If an interrupt comes in during a barrier, it is abandoned/restarted. Cycle count information: • P = pipeline reload • N = count of elements ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 18-5 Non-Confidential Unrestricted Access...
  • Page 360 In general, each instruction takes one cycle (one core clock) to start executing as Table 18-1 on page 18-3 shows. Additional cycles can be taken because of fetch stalls. 18-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential...

  • Page 361: Load-Store Timings

    LDR R0,[R1,R2]; STR R0,[R3,#20] - normally three cycles total — LDR R0,[R1,R2]; STR R1,[R3,R2] - normally three cycles total — LDR R0,[R1,R5]; LDR R1,[R2]; LDR R2,[R3,#4] - normally four cycles total. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 18-7 Non-Confidential Unrestricted Access...
  • Page 362 These numbers increase if the memory stalls. A STR or STRH cannot delay the processor because of the store buffer. 18-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 363: Chapter 19 Ac Characteristics

    Chapter 19 AC Characteristics This chapter gives the timing parameters for the processor. It contains the following sections: • Processor timing parameters on page 19-2. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-1 Non-Confidential Unrestricted Access...

  • Page 364: Processor Timing Parameters

    Table 19-2 shows the timing parameters for the low power input ports. Table 19-2 Low power input ports timing parameters Input delay Min. Input delay Max. Signal name Clock uncertainty SLEEPHOLDREQn Clock uncertainty WICDSREQn 19-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 365: Table 19-3 Interrupt Input Ports Timing Parameters

    HRESPI[1:0] Clock uncertainty HRDATAD[31:0] Clock uncertainty HREADYD Clock uncertainty HRESPD[1:0] Clock uncertainty EXRESPD Clock uncertainty HRDATAS[31:0] Clock uncertainty HREADYS Clock uncertainty HRESPS[1:0] Clock uncertainty EXRESPS ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-3 Non-Confidential Unrestricted Access...

  • Page 366: Table 19-5 Ppb Input Port Timing Parameters

    DAPENABLE Clock uncertainty DAPCLKEN Clock uncertainty DAPWRITE Clock uncertainty DAPABORT Clock uncertainty DAPADDR[31:0] Clock uncertainty DAPWDATA[31:0] Clock uncertainty ATREADY Clock uncertainty DBGRESTART Clock uncertainty FIXHMASTERTYPE 19-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 367: Table 19-7 Test Input Ports Timing Parameters

    Output delay Min. Output delay Max. Signal name Clock uncertainty LOCKUP Clock uncertainty SYSRESETREQ Clock uncertainty BRCHSTAT[3:0] Clock uncertainty HALTED Clock uncertainty TXEV Clock uncertainty ATIDITM[6:0] ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-5 Non-Confidential Unrestricted Access...

  • Page 368: Table 19-10 Low Power Output Ports Timing Parameters

    Table 19-11 AHB output ports timing parameters Output delay Min. Output delay Max. Signal name Clock uncertainty HTRANSI[1:0] Clock uncertainty HSIZEI[2:0] Clock uncertainty HPROTI[3:0] Clock uncertainty MEMATTRI[1:0] 19-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 369 HSIZES[2:0] Clock uncertainty HPROTS[3:0] Clock uncertainty MEMATTRS[1:0] Clock uncertainty EXREQS Clock uncertainty HBURSTS[2:0] Clock uncertainty HMASTLOCKS Clock uncertainty HADDRS[31:0] Clock uncertainty HWDATAS[31:0] Clock uncertainty HWRITES ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-7 Non-Confidential Unrestricted Access...

  • Page 370: Table 19-12 Ppb Output Ports Timing Parameters

    Clock uncertainty SWDOEN Clock uncertainty DAPREADY Clock uncertainty DAPSLVERR Clock uncertainty DAPRDATA[31:0] Clock uncertainty ATVALID Clock uncertainty AFREADY Clock uncertainty ATDATA[7:0] Clock uncertainty DBGRESTARTED 19-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 371: Table 19-14 Etm Interface Output Ports Timing Parameters

    Table 19-15 HTM interface output ports timing parameters Output delay Min. Output delay Max. Signal name Clock uncertainty HTMDHADDR[31:0] Clock uncertainty HTMDHTRANS[1:0] Clock uncertainty HTMDHSIZE[2:0] ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-9 Non-Confidential Unrestricted Access...

  • Page 372: Table 19-16 Test Output Ports Timing Parameters

    Table 19-16 shows the timing parameters for the test output ports. Table 19-16 Test output ports timing parameters Output delay Min. Output delay Max. Signal name Clock uncertainty Clock uncertainty WSOO Clock uncertainty WSIO 19-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 373 • ETM interface on page A-14 • AHB Trace Macrocell interface on page A-16 • Test interface on page A-17 • WIC interface on page A-18. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 374: Appendix A Signal Descriptions

    Table A-1 lists the clock signals. Table A-1 Clock signals Name Direction Description HCLK Input Main Cortex-M3 clock FCLK Input Free-running Cortex-M3 clock DAPCLK Input AHB-AP clock Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 375: Resets

    System reset. Resets processor, non-debug portion of NVIC, Bus Matrix, and MPU. Debug components are not reset. SYSRESETREQ Output System reset request. DAPRESETn Input AHB-AP reset. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 376: Miscellaneous

    Input System Tick Clock. STCALIB[25:0] Input System Tick Calibration. RXEV Input Causes a wakeup from a WFE instruction. VECTADDR[9:0] Input Reserved. Must be tied to 10'b0000000000. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 377 AUXFAULT[31:0] Input Auxiliary fault status information from the system. IFLUSH Input Reserved. Instruction flush, must be tied to 0. DBGRESTART Input External restart request. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 378: Interrupt Interface

    Table A-4 lists the signals of the external interrupt interface. Table A-4 Interrupt interface signals Name Direction Description INTISR[239:0] Input External interrupt signals INTNMI Input Non-maskable interrupt Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 379: Low Power Interface

    Table A-5 lists the signals of the low power interface. Table A-5 Low power interface signals Name Direction Description SLEEPDEEP Output Indicates that the Cortex-M3 clock can be stopped. SLEEPING Output Indicates that the Cortex-M3 clock can be stopped. SLEEPHOLDACKn Output Acknowledge signal for SLEEPHOLDREQn.

  • Page 380: Icode Interface

    When HIGH indicates that a transfer has completed on the bus. This signal is driven LOW to extend a transfer. HRESPI[1:0] Input The transfer response status. OKAY or ERROR. Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 381: Dcode Interface

    When HIGH indicates that a transfer has completed on the bus. This signal is driven LOW to extend a transfer. HRESPD[1:0] Input The transfer response status. OKAY or ERROR. HRDATAD[31:0] Input Read data. EXRESPD Input Exclusive response. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...

  • Page 382: System Bus Interface

    When HIGH indicates that a transfer has completed on the bus. The signal is driven LOW to extend a transfer. HRESPS[1:0] Input The transfer response status. OKAY or ERROR. EXRESPS Input Exclusive response. A-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 383: Private Peripheral Bus Interface

    Output 32-bit write data bus. PWRITE Output Write not read. PRDATA[31:0] Input Read data bus. PREADY Input APB slave ready. PSLVERR Input APB slave error. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-11 Non-Confidential Unrestricted Access...

  • Page 384: Itm Interface

    Input TPIU active indication signal. TPIUBAUD Input Reference for the timestamp counter, so that timestamps are at the observable baud rate of the external protocol. A-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 385: Ahb-Ap Interface

    Status Word (CSW). This ensures accesses from the debugger is always issued as on HMASTERD and HMASTERS regardless of the MasterType setting in the CSW. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-13 Non-Confidential Unrestricted Access...

  • Page 386: Etm Interface

    ETM is enabled ETMDVALID Output Data valid ETMCANCEL Output Instruction cancelled ETMFINDBR Output Flush is indirect. Marks flush hint destination cannot be inferred from the PC. A-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 387 ETM FIFO is full, and causes the processor to stall until the FIFO has drained, so ensuring that no trace is lost. DSYNC Output Synchronization pulse from DWT. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-15 Non-Confidential Unrestricted Access...

  • Page 388: Ahb Trace Macrocell Interface

    32-bit write data bus. HTMDHWRITE Output Write not read. HTMDHRDATA[31:0] Output Read data bus. HTMDHREADY Output Ready signal. HTMDHRESP[1:0] Output The transfer response status. OKAY or ERROR. A-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 389: Test Interface

    RSTBYPASS Input Reset bypass for scan testing. PORESETn is the only reset used during scan testing. CGBYPASS Input Architectural clock gate bypass for scan testing. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-17 Non-Confidential Unrestricted Access...

  • Page 390: Wic Interface

    Clear sensitivity list in WIC. WICENREQ Input Make SLEEPDEEP mode WIC mode sleep request from PMU. WICDSACKn Input Active low SLEEPDEEP is WICSLEEP acknowledgement from NVIC. A-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 391: Appendix B Revisions

    Addition of note to SW/SWJ-DP subsection • ROM table subsection. Introductory processor core information updated Processor core on page 1-5 APB bus now version 3.0 Bus matrix on page 1-7 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 392 Debug Core Register Selector Register REGSEL bit field Table 10-3 on page 10-7 function updated Extra paragraph added. About system debug on page 11-2 Paragraph added about removing FPB FPB on page 11-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 393 Table 14-2 on page 14-4, Table 14-3 on page 14-5, Table 14-4 on page 14-5, Table 14-5 on page 14-6, and Table 14-6 on page 14-6 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 394 Branch status interface on page 15-6 Example of an opcode sequence timing diagram updated Figure 15-9 on page 15-13 Description of APB interface inputs added APB interface on page 17-7 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...

  • Page 395: Table B-2 Differences Between Issue F And Issue G

    • CID registers Table B-2 Differences between issue F and issue G Change Location Wake-up Interrupt Controller (WIC) added to Cortex-M3 block Figure 1-1 on page 1-5 diagram Section 1-2 and section 1-3 combined Components, hierarchy, and implementation on page 1-4...
  • Page 396 Table 19-12 on page 19-8 to Table 19-16 on page 19-10 inclusive SLEEPING, SLEEPDEEP, and SLEEPHOLDACKn removed Miscellaneous output ports timing parameters on from table of miscellaneous output ports timing parameters page 19-5 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 397 Table A-5 on page A-7 SLEEPHOLDREQn in table of low power interface signals FIXMASTERTPYE added to list of AHB-AP interface signals Table A-11 on page A-13 ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access...
  • Page 398 Revisions Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 399 Glossary This glossary describes some of the terms used in technical documents from ARM. A mechanism that indicates to a core that the attempted memory access is invalid or not Abort allowed or that the data returned by the memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid or protected instruction or data memory.
  • Page 400 A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
  • Page 401 An instruction of the ARM Instruction Set Architecture (ISA). These cannot be ARM instruction executed by the Cortex-M3. The processor state in which the processor executes the instructions of the ARM ISA. ARM state The processor only operates in Thumb state, never in ARM state.
  • Page 402 See also Beat. An 8-bit data item. Byte Glossary-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 403 The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported.
  • Page 404 The formatter is an internal input block in the ETB and TPIU that embeds the trace Formatter source ID within the data to create a single trace stream. A 16-bit data item. Halfword Glossary-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 405 The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Glossary-7 Non-Confidential Unrestricted Access...
  • Page 406 Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not modify addresses. Glossary-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 407 The PFU buffers up to three word fetches in its FIFO, which means that it can buffer up to three 32-bit Thumb instructions or six 16-bit Thumb instructions. ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Glossary-9 Non-Confidential...
  • Page 408 An optional external interface for the DAP that provides a serial-wire bidirectional debug interface. A standard debug port that combines JTAG-DP and SW-DP. Serial-Wire JTAG Debug Port See Serial-Wire Debug Port. SW-DP Glossary-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G Non-Confidential Unrestricted Access...
  • Page 409 Thread Control Block a single thread of execution. A halfword that specifies an operation for an ARM processor in Thumb state to Thumb instruction perform. Thumb instructions must be halfword-aligned. A processor that is executing Thumb (16-bit) halfword aligned instructions is operating Thumb state in Thumb state.
  • Page 410 The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged. The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions that are given unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access.

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