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Exception vector
Exponent
External Abort
Fast context switch
Fast Context Switch Extension (FCSE)
FCSE
Fd
Flat address mapping
Flush-to-zero mode
Fm
Fn
Fraction
ARM DDI 0301H
ID012310
See Interrupt vector.
The component of a floating-point number that normally signifies the integer power to which
two is raised in determining the value of the represented number.
An indication from an external memory system to a core that it must halt execution of an
attempted illegal memory access. An External Abort is caused by the external memory system
as a result of attempting to access invalid memory.
See also Abort, Data Abort and Prefetch Abort.
In a multitasking system, the point at which the time-slice allocated to one process stops and the
one for the next process starts. If processes are switched often enough, they can appear to a user
to be running in parallel, in addition to being able to respond quicker to external events that
might affect them.
In ARM processors, a fast context switch is caused by the selection of a non-zero PID value to
switch the context to that of the next process. A fast context switch causes each Virtual Address
for a memory access, generated by the ARM processor, to produce a Modified Virtual Address
which is sent to the rest of the memory system to be used in place of a normal Virtual Address.
For some cache control operations Virtual Addresses are passed to the memory system as data.
In these cases no address modification takes place.
See also Fast Context Switch Extension.
An extension to the ARM architecture that enables cached processors with an MMU to present
different addresses to the rest of the memory system for different software processes, even when
those processes are using identical addresses.
See also Fast context switch.
See Fast Context Switch Extension.
The destination register and the accumulate value in triadic operations. Sd for single-precision
operations and Dd for double-precision.
A system of organizing memory in which each Physical Address contained within the memory
space is the same as its corresponding Virtual Address.
In this mode, the VFP11 coprocessor treats the following values as positive zeros:
•
arithmetic operation inputs that are in the subnormal range for the input precision
•
arithmetic operation results, other than computed zero results, that are in the subnormal
range for the input precision before rounding.
The VFP11 coprocessor does not interpret these values as subnormal values or convert them to
subnormal values.
The subnormal range for the input precision is –2
The second source operand in dyadic or triadic operations. Sm for single-precision operations
and Dm for double-precision.
The first source operand in dyadic or triadic operations. Sn for single-precision operations and
Dn for double-precision.
The floating-point field that lies to the right of the implied binary point.
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Emin
Emin
< x < 0 or 0< x < 2
Glossary
.
Glossary-11
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