Figure 13-2 Debug Id Register Format - ARM ARM1176JZF-S Technical Reference Manual

13.3.2 CP14 c0, Debug ID Register (DIDR)
ARM DDI 0301H
ID012310
Binary address
Opcode_2 CRm
b000 b0110
b000 b0111
b000 b1000-b1001
b000 b1010
b000 b1011
b000 b1100-b1111
b001-b011 b0000-b1111
b100 b0000-b0101
b0110-b111
b101 b0000-b0101
b0110-b1111
b110 b0000-b0001
b0010-b1111
b111 b0000-b0001
b0010-b1111
a. y is the decimal representation for the binary number CRm.
Note
All the debug resources required for Monitor debug-mode debugging are accessible through
CP14 registers. For Halting debug-mode debugging some additional resources are required. See
Chapter 14 Debug Test Access Port.
The Debug ID Register is a read-only register that defines the configuration of debug registers
in a system. Figure 13-2 shows the format of the Debug ID Register.
31 28 27 24 23
WRP BRP
For the ARM1176JZF-S processor:
• DIDR[31:8] has the value 0x15121x
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Table 13-2 CP14 debug register map (continued)
Register
CP14 debug register name
number
c6 Watchpoint Fault Address Register
c7 Vector Catch Register
c8-c9 Reserved
c10 Debug State Cache Control Register
c11 Debug State MMU Control Register
c12-c15 Reserved
c16-c63 Reserved
c64-c69 Breakpoint Value Registers
c70-c79 Reserved
c80-c85 Breakpoint Control Registers
c86-c95 Reserved
c96-c97 Watchpoint Value Registers
c98-c111 Reserved
c112-c113 Watchpoint Control Registers
c114-c127 Reserved
20 19 16 15
Context Version
Debug architecture revision
Abbreviation
WFAR
VCR
-
DSCCR
DSMCR
-
-
BVRy
-
BCRy
-
WVRy
-
WCRy
-
12 11 8 7
UNP/SBZ Variant

Figure 13-2 Debug ID Register format

Debug
a
a
a
a
4 3 0
Revision
13-6