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2.10.2
The Q flag
2.10.3
The J bit
ARM DDI 0301H
ID012310
•
SETEND
•
RFE
•
SRS
•
STC2.
In Thumb state, only the Branch instruction can be executed conditionally. For more
information about conditional execution, see the ARM Architecture Reference Manual.
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic
instructions:
•
QADD
•
QDADD
•
QSUB
•
QDSUB
•
SMLAD
•
SMLAxy
•
SMLAWy
•
SMLSD
•
SMUAD
•
SSAT
•
SSAT16
•
USAT
•
USAT16.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by
an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status
of the Q flag.
To determine the status of the Q flag you must read the PSR into a register and extract the Q flag
from this. For details of how the Q flag is set and cleared, see individual instruction definitions
in the ARM Architecture Reference Manual.
The J bit in the CPSR indicates when the processor is in Jazelle state.
When:
J = 0
The processor is in ARM or Thumb state, depending on the T bit.
J = 1
The processor is in Jazelle state.
Note
•
The combination of J = 1 and T = 1 causes similar effects to setting T=1 on a non
Thumb-aware processor. That is, the next instruction executed causes entry to the
Undefined Instruction exception. Entry to the exception handler causes the processor to
re-enter ARM state, and the handler can detect that this was the cause of the exception
because J and T are both set in SPSR_und.
•
MSR cannot be used to change the J bit in the CPSR.
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