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14.7
Using the Debug Test Access Port
14.7.1
Entering and leaving Debug state
14.7.2
Executing instructions in Debug state
ARM DDI 0301H
ID012310
This section contains the following subsections:
•
Entering and leaving Debug state
•
Executing instructions in Debug state
•
Using the ITRsel IR instruction on page 14-22
•
Transferring data between the host and the core on page 14-23
•
Using the debug communications channel on page 14-23
•
Target to host debug communications channel sequence on page 14-24
•
Host to target debug communications channel on page 14-24
•
Transferring data in Debug state on page 14-25
•
Example sequences on page 14-26.
Debug sequences on page 14-29 describes these debug sequences in detail.
When the processor is in Debug state, it can be forced to execute ARM state instructions using
the DBGTAP. Two registers are used for this purpose, the Instruction Transfer Register (ITR)
and the Data Transfer Register (DTR). The ITR is used to insert an instruction into the processor
pipeline. An ARM state instruction can be loaded into this register using scan chain number 4.
When the instruction is loaded, and INTEST or EXTEST is selected, and scan chain 4 or 5 is
selected, the instruction can be issued to the core by making the DBGTAPSM go through the
Run-Test/Idle state, provided certain conditions, that this section describes, are met. This
mechanism enables re-executing the same instruction over and over without having to reload it.
The DTR can be used in conjunction with the ITR to transfer data in and out of the core. For
example, to read out the value of an ARM register:
1.
issue an
MCR p14,0,Rd,c0,c5,0
c5 register
2.
scan out the wDTR.
The DSCR[13] execute ARM instruction enable bit controls the activation of the ARM
instruction execution mechanism. If this bit is cleared, no instruction is issued to the core when
the DBGTAPSM goes through Run-Test/Idle. Setting this bit while the core is not in Debug state
leads to Unpredictable behavior. If the core is in Debug state and this bit is set, the Ready and
the sticky precise Data Abort flags condition the updates of the ITR and the instruction issuing,
as Scan chain 4, instruction transfer register (ITR) on page 14-13 describes. As an example, this
sequence stores out the contents of the ARM register R0:
1.
Scan_N into the IR.
2.
1 into the SCREG.
3.
INTEST into the IR.
4.
Scan out the contents of the DSCR. This action clears the sticky precise Data Abort and
sticky imprecise Data Abort flags and sticky Undefined bit.
5.
EXTEST into the IR.
6.
Scan in the previously read value with the DSCR[13] execute ARM instruction enable bit
set.
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instruction to the core to transfer the
Debug Test Access Port
<Rd>
contents to the
14-21
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