Table of Contents
Advertisement
Bits
Core view
[18]
R
[17]
R
[16]
R
[15]
RW
[14]
R
[13]
R
[12]
RW
[11]
R
[10]
R
[9]
R
ARM DDI 0301H
ID012310
Table 13-4 Debug Status and Control Register bit field definitions (continued)
External
Reset
Description
view
value
R
0
Non-secure World Status bit 0 = The processor is in Secure state. NS
bit = 0 or Secure Monitor mode.1 = The processor is in Non-secure
state. NS bit = 1 and not Secure Monitor mode.
Not Secure Privilege Non-Invasive Debug Enable, SPNIDEN, input
R
n/a
pin.0 = SPNIDEN input pin is HIGH.1 = SPNIDEN input pin is LOW.
Not Secure Privilege Invasive Debug Enable, SPIDEN, input pin.0 =
R
n/a
SPIDEN input pin is HIGH.1 = SPIDEN input pin is LOW.
R
0
The Monitor debug-mode enable bit:
0 = Monitor debug-mode disabled
1 = Monitor debug-mode enabled.
For the core to take a debug exception, Monitor debug-mode has to be
both selected and enabled, bit 14 clear and bit 15 set.
RW
0
Mode select bit:
0 = Monitor debug-mode selected
1 = Halting debug-mode selected and enabled.
RW
0
Execute ARM instruction enable bit:
0 = Disabled
1 = Enabled.
If this bit is set, the core can be forced to execute ARM instructions in
Debug state using the Debug Test Access Port. If this bit is set when
the core is not in Debug state, the behavior of the processor is
architecturally Unpredictable. For ARM1176JZF-S processors it has
no effect.
R
0
User mode access to comms channel control bit:
0 = User mode access to comms channel enabled
1 = User mode access to comms channel disabled.
If this bit is set and a User mode process tries to access the DIDR,
DSCR, or the DTR, the Undefined instruction exception is taken.
Because accessing the rest of CP14 debug registers is never possible
in User mode, see Executing CP14 debug instructions on page 13-27,
setting this bit means that a User mode process cannot access any
CP14 debug register.
RW
0
Interrupts bit:
0 = Interrupts enabled
1 = Interrupts disabled.
If this bit is set, the IRQ and FIQ input signals are inhibited.
RW
0
DbgAck bit.
If this bit is set, the DBGACK output signal (see External signals on
page 13-52) is forced HIGH, regardless of the processor state.
RW
0
Powerdown disable:
0 = DBGNOPWRDWN is LOW
1 = DBGNOPWRDWN is HIGH.
See External signals on page 13-52.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Debug
a
a
13-9
Hide quick links:
Advertisement
Table of Contents
