ARM ARM1176JZF-S Technical Reference Manual page 300

Table 4-3 Unalignment fault occurrence when access behavior is architecturally unpredictable (continued)
A U Addr[2:0]
0 1 bxxx
0 1 bxx0
0 1 bxx1
0 1 bxxx
0 1 bx00
0 1 bxx1, bx1x
0 1 b000
0 1 bxx1,
bx1x, b1xx
1 x -
1 x bxxx
1 x bxx0
1 x bxx1
1 x bx00
1 x bxx1, bx1x
1 x b000
1 0 b100
1 1 b100
1 x bxx1, bx1x
1 x b000
1 x bxx1,
bx1x, b1xx
ARM DDI 0301H
ID012310
Access Architectural
types Behavior
Halfword Normal
HWSync Normal
HWSync Alignment fault
Wload, Normal
WStore
WSync, Normal
Multi-word,
Two-word
WSync, Alignment fault
Multi-word,
Two-word
DWSync Normal
DWSync Alignment fault
- -
Byte, BSync Normal
Halfword, Normal
HWSync
Halfword, Alignment fault
HWSync
WLoad, Normal
WStore,
WSync,
Multi-word
WLoad, Alignment fault
WStore,
WSync,
Multi-word
Two-word Normal
Two-word Alignment fault
Two-word Normal
Two-word Alignment fault
DWSync Normal
DWSync Alignment fault
The following causes override the behavior specified in the Table 4-3 on page 4-14:
• An LDR instruction that loads the PC, has Addr[1:0] != b00, and is specified in the table
as having Normal behavior instead has Unpredictable behavior.
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Unaligned and Mixed-endian Data Access Support
Memory accessed Note
Halfword[Addr]
Halfword[Addr]
Word[Addr]
Word[Addr]
- -
Word[Addr]
-
- Full alignment faulting
Byte[Addr]
Halfword[Addr]
-
Word[Addr]
-
Word[Addr]
-
Word[Addr]
-
Word[Addr]
-
4-15