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V bit
0
1
3.2.53
c15, Count Register 0
ARM DDI 0301H
ID012310
Access to the Cycle Counter Register in User mode depends on the V bit, see c15, Secure User
and Non-secure Access Validation Control Register on page 3-132. The Cycle Counter Register
is always accessible in Privileged modes. Table 3-139 lists the results of attempted access for
each mode.
Secure Privileged
Read
Write
Data
Data
Data
Data
To access the Cycle Counter Register read or write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c15
•
CRm set to c12
•
Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c15, c12, 1
MCR p15, 0, <Rd>, c15, c12, 1
The value in the Cycle Counter Register is zero at Reset.
You can use the Performance Monitor Control Register to set the Cycle Counter Register to zero.
You can use the Performance Monitor Control Register to configure the Cycle Counter Register
to count every 64th clock cycle.
The purpose of the Count Register 0 is to count instances of an event that the Performance
Monitor Control Register selects.
The Count Register 0:
•
is in CP15 c15
•
is a 32-bit read/write register common to Secure and Non-secure worlds
•
counts up and can trigger an interrupt on overflow.
Count Register 0 bits [31:0] contain the count value. The reset value is 0.
You can use this register in conjunction with the Performance Monitor Control Register, the
Cycle Count Register, and Count Register 1 to provide a variety of useful metrics that enable
you to optimize system performance.
Note
•
In Debug state the counter is disabled.
When the core is in a mode where noninvasive debug is not permitted, set by SPNIDEN
•
and the SUNIDEN bit, see c1, Secure Debug Enable Register on page 3-54, the processor
does not count events.
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Non-Confidential, Unrestricted Access
Table 3-139 Results of access to the Cycle Counter Register
Non-secure Privileged
Read
Write
Data
Data
Data
Data
; Read Cycle Counter Register
; Write Cycle Counter Register
System Control Coprocessor
User
Read
Write
Undefined exception
Undefined exception
Data
Data
3-138
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