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16.2
Register interlock examples
Instruction sequence
LDR R1, [R2]
ADD R6, R5, R4
ADD R1, R2, R3
ADD R9, R6, R1
LDR R1, [R2]
ADD R6, R5, R1
ADD R1, R5, R6
LDR R2, [R1]
LDR R1, [R2]
LDR R5, [R1]
ARM DDI 0301H
ID012310
Table 16-3 lists register interlock examples using LDR and ADD instructions.
LDR instructions take one cycle, have a result latency of three, and require their base register as
an Early Reg.
ADD instructions take one cycle and have a result latency of one.
Behavior
Takes two cycles because there are no register dependencies
Takes two cycles because ADD instructions have a result latency of one
Takes four cycles because of the result latency of R1
Takes three cycles because of the use of the result of R1 as an Early Reg
Takes five cycles because of the result latency and the use of the result of R1 as an Early Reg
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Cycle Timings and Interlock Behavior
Table 16-3 Register interlock examples
16-6
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