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ARM DDI 0301H
ID012310
When maximum performance is required, SYNCMODEREQ is asserted. When the IEM
register slice receives this signal it closes its FIFOs to new data, subject to the constraints
required by the AXI protocol, waits for the FIFOs to drain, and then switches the multiplexers
so that the AXI master and slave connect directly. The IEM register slice asserts
SYNCMODEACK to acknowledge the direct connection.
For reduced performance levels SYNCMODEREQ is deasserted, and the IEM register slice
switches the muxltiplexers and deasserts SYNCMODEACK when it has done so. The protocol
for these signals means that it is possible to connect different IEM register slices together. You
can connect SYNCMODEREQ to all the IEM register slices in parallel and AND together the
SYNCMODEACK outputs.
This means that the SYNCMODEACK signal only goes high when all the IEM register slices
have asserted their SYNCMODEACK signals. When coming out of bypass mode, all the IEM
registers slices take the same number of cycles, so the SYNCMODEACK signals all deassert
at the same time. Alternatively, if necessary, you can daisy chain the IEM register slices together,
so that each slice in the chain only closes its inputs when the previous slice has been multiplexed
out.
Read latency penalty for synchronous operation with IEM
When the IEM register slices are instantiated, but are synchronous because SYNCMODEREQ
is asserted, the read latency is the same as if the IEM register slices were not present. See Read
latency penalty with no IEM on page 9-3 and Figure 9-2 on page 9-4.
Read latency penalty for asynchronous operation with IEM
When the IEM register slices are instantiated and in asynchronous mode, data read or write
operations incur additional latency because of the synchronization required for the address and
the data between the core and the AXI system. The exact latency depends on:
•
the clock ratios
•
the clock alignments
•
the latency of the AXI system.
On average, with zero-wait-state AXI the system incurs a penalty of 2.5 additional CLKIN
cycles and 4.5 additional ACLK cycles.
Figure 9-5 on page 9-8 shows the latency that the IEM register slices add in a system with
ACLK and CLKIN of the same frequency, but not synchronous. This example AXI system is
zero-wait-state.
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Clocking and Resets
9-7
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