Table of Contents
Advertisement
22.4
Exception processing
22.4.1
Determination of the trigger instruction
22.4.2
Exception processing for CDP scalar instructions
22.4.3
Exception processing for CDP short vector instructions
ARM DDI 0301H
ID012310
The ARM11/VFP11 interface specifies that an exceptional instruction that bounces to support
code must signal on a subsequent coprocessor instruction. This is known as imprecise exception
handling. It means that when the exception is processed, the VFP11 and ARM11 user states
might be different from their states when the exceptional instruction executed. Parallel
execution of VFP11 CDP instructions and data transfer instructions enables the VFP11 and
ARM11 register files and memory to be modified outside of the program order.
The issue timing of VFP11 instructions affects the determination of the trigger instruction. The
last iteration of a short vector CDP can be followed in the next cycle by a second CDP
instruction. If there is no hazard, the VFP11 coprocessor accepts the second CDP instruction
before the exception status of the last iteration of the short vector CDP is known. The second
CDP instruction is said to be in the pretrigger slot and is retained in the FPINST2 register for
the support code.
The following rules determine the instruction that is the trigger instruction:
•
The first nonserializing instruction after the exceptional condition has been detected is the
trigger instruction.
•
An instruction that accesses the FPSCR register in any processor mode is a trigger
instruction.
•
An instruction that accesses the FPEXC, FPINST, or FPINST2 register in a privileged
mode is not a trigger instruction.
•
An instruction that accesses the FPSID register in any mode is not a trigger instruction.
•
A data processing instruction that reaches the LS pipeline Execute stage or a CDP
instruction that reaches the FMAC or DS pipeline E1 stage is not the trigger instruction.
There can be several of these if the exceptional instruction is a sufficiently long short
vector instruction, and the exception is detected on a later iteration.
When the VFP11 coprocessor detects an exceptional scalar CDP instruction, it loads the
FPINST register with the instruction word for the exceptional instruction and flags the condition
in the FPEXC register. It blocks the exceptional instruction from additional execution and
completes any instructions currently executing in the FMAC and DS pipelines.
It then examines the pipeline for a trigger instruction:
•
If there is a VFP CDP instruction or a load or store instruction in the VFP11 Issue stage,
it is the trigger instruction and is bounced in the cycle after the exception is detected.
•
If there is no VFP instruction in the VFP11 Issue stage, the VFP11 coprocessor waits until
one is issued. The next VFP instruction is the trigger instruction and is bounced.
When the ARM11 processor returns from exception processing, it retries the trigger instruction.
For short vector instructions, any iteration might be exceptional. If an exceptional condition is
detected for a vector iteration, the vector iterations issued before the exceptional iteration are
permitted to complete and retire.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
VFP Exception Handling
22-8
Hide quick links:
Advertisement
Table of Contents
