ARM ARM1176JZF-S Technical Reference Manual page 123

ARM DDI 0301H
ID012310
PC = Non_Secure_Base_Address + 0x00000008
External Prefetch Abort
On an external prefetch abort:
if SCR[3]=1 /* external prefetch aborts trapped to Secure Monitor mode */
R14_mon = address of the aborted instruction + 4
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of Secure Ctrl Reg bit[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x0000000C
Else
R14_abt = address of the aborted instruction + 4
SPSR_abt = CPSR
CPSR [4:0] = 0b10111 /* Enter abort mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
If SCR[5]=1 (bit AW)
CPSR [8] = 1 /* Disable imprecise aborts */
Else
CPSR [8] = UNCHANGED
CPSR [9] = Non-secure EE-bit /* store value of NS Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF000C
else
PC = Non_Secure_Base_Address + 0x0000000C
Internal Prefetch Abort
On an internal prefetch abort:
/* Non-secure state is unchanged */
R14_abt = address of the aborted instruction + 4
SPSR_abt = CPSR
CPSR [4:0] = 0b10111 /* Enter abort mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
If SCR[5]=1 (bit AW)
CPSR [8] = 1 /* Disable imprecise aborts */
Else
CPSR [8] = UNCHANGED
CPSR [9] = Non-secure EE-bit /* store value of NS Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF000C
else
PC = Non_Secure_Base_Address + 0x0000000C
External Data Abort
On an External Precise Data Abort or on an External Imprecise Abort with CPSR[8]=0 (A bit):
/* Non-secure state is unchanged */
if SCR[3]=1 /* external aborts trapped to Secure Monitor mode */
R14_mon = address of the aborted instruction + 8
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
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