Table 3-33 Results Of Access To The Instruction Set Attributes Register 2; Figure 3-24 Instruction Set Attributes Register 3 Format - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[11:8] -
[7:4] -
[3:0] -
ARM DDI 0301H
ID012310
Table 3-32 Instruction Set Attributes Register 2 bit functions (continued)
Function
Indicates support for multi-access interruptible instructions.
, ARM1176JZF-S processors support restartable LDM and STM.
0x1
Indicates support for memory hint instructions.
, ARM1176JZF-S processors support PLD.
0x2
Indicates support for load and store instructions.
0x1 , ARM1176JZF-S processors support LDRD and STRD.
Table 3-33 lists the results of attempted access for each mode.

Table 3-33 Results of access to the Instruction Set Attributes Register 2

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 2 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c0, c2, 2 ;Read Instruction Set Attributes Register 2
c0, Instruction Set Attributes Register 3
The purpose of the Instruction Set Attributes Register 3 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 3 is:
• in CP15 c0
• a 32-bit read-only registers common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-24 shows the bit arrangement for Instruction Set Attributes Register 3.
31 28 27 24 23
- -
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Data Undefined exception
20 19 16 15
- - -

Figure 3-24 Instruction Set Attributes Register 3 format

System Control Coprocessor
User
Undefined exception
12 11 8 7 4 3
- -
0
-
3-40