ARM Cortex A9 Technical Reference Manual
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ARM Cortex A9 Technical Reference Manual

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Cortex
-A9
™
Revision: r4p1
Technical Reference Manual
Copyright © 2008-2012 ARM. All rights reserved.
ARM DDI 0388I (ID073015)

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  • Page 1 Cortex ™ Revision: r4p1 Technical Reference Manual Copyright © 2008-2012 ARM. All rights reserved. ARM DDI 0388I (ID073015)
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    About the programmers model ................3-2 ThumbEE architecture ..................... 3-3 The Jazelle Extension ....................3-4 Advanced SIMD architecture ................... 3-5 Security Extensions architecture ................3-6 Multiprocessing Extensions ..................3-7 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 4 About the Performance Monitoring Unit ..............11-2 11.2 PMU register summary ..................11-3 11.3 PMU management registers .................. 11-5 11.4 Performance monitoring events ................11-7 Appendix A Signal Descriptions Clock signals ......................A-2 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 5 About instruction cycle timing .................. B-2 Data-processing instructions ................... B-3 Load and store instructions ..................B-4 Multiplication instructions ..................B-7 Branch instructions ....................B-8 Serializing instructions ..................... B-9 Appendix C Revisions ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 6 Preface This preface introduces the Cortex-A9 Technical Reference Manual (TRM). It contains the following sections: • About this book on page vii • Feedback on page ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 7: Preface

    Read this for a description of the Cortex-A9 Memory Management Unit (MMU). Chapter 7 Level 1 Memory System Read this for a description of the Cortex-A9 level one memory system, including caches, Translation Lookaside Buffers (TLB), and store buffer. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 8 Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

  • Page 9: Timing Diagrams

    LOW for active-LOW signals. Lower-case n At the start or end of a signal name denotes an active-LOW signal. Additional reading This section lists publications by ARM and by third parties. See Infocenter, , for access to ARM documentation. http://infocenter.arm.com ARM DDI 0388I Copyright ©...
  • Page 10 This book contains information that is specific to this product. See the following documents for other relevant information: • ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406) • Cortex-A9 MPCore Technical Reference Manual (ARM DDI 0407) •...

  • Page 11: Feedback

    ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. ARM DDI 0388I Copyright ©...
  • Page 12 Interfaces on page 1-7 • Configurable options on page 1-8 • Test features on page 1-9 • Product documentation and design flow on page 1-10 • Product revisions on page 1-12. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 13: Chapter 1 Introduction

    Introduction About the Cortex-A9 processor The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements the ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle state.
  • Page 14 The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of improving the performance of ARM-based systems when significant memory traffic is generated by the processor. The CoreLink Level 2 Cache Controller reduces the number of external memory accesses and has been optimized for use with Cortex-A9 processors and Cortex-A9 MPCore processors.

  • Page 15: Cortex-A9 Variants

    Cortex-A9 MPCore AXI master interfaces — Cortex-A9 uniprocessor accesses to private memory regions. • an Interrupt Controller (IC) with support for legacy ARM interrupts • a private timer and a private watchdog per processor • a global timer •...

  • Page 16: Compliance

    The Cortex-A9 processor implements the ARMv7 Debug architecture that includes support for Security Extensions and CoreSight. See the CoreSight Architecture Specification. 1.3.5 Generic Interrupt Controller architecture The Cortex-A9 processor implements the ARM Generic Interrupt Controller (GIC) v1.0 architecture. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.

  • Page 17: Features

    The Cortex-A9 processor includes the following features: • superscalar, variable length, out-of-order pipeline with dynamic branch prediction • full implementation of the ARM architecture v7-A instruction set • Security Extensions • Harvard level 1 memory system with Memory Management Unit (MMU).

  • Page 18: Interfaces

    Debug v7 compliant interface, including a debug APBv3 external debug interface • DFT. For more information on these interfaces see: • AMBA AXI Protocol Specification • CoreSight Architecture Specification • Cortex-A9 MBIST Controller Technical Reference Manual ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 19: Configurable Options

    MPE RTL option is not implemented, you can implement the VFPv3-D16 FPU by choosing the FPU RTL option. b. The Cortex A9 processor does not support Parity error detection on the GHB RAMs, for GHB configurations of 8192 and 16384 entries.

  • Page 20: Test Features

    The Cortex-A9 processor provides test signals that enable the use of both ATPG and MBIST to test the Cortex-A9 processor and its memory arrays. See Appendix A Signal Descriptions the Cortex-A9 MBIST Controller Technical Reference Manual. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 21: Product Documentation And Design Flow

    • the processes to sign off the configured design. The ARM product deliverables include reference scripts and information about using them to implement your design. Reference methodology documentation from your EDA tools vendor complements the CSG.
  • Page 22 Reference to a feature that is included mean that the appropriate build and pin configuration options are selected. Reference to an enabled feature means one that has also been configured by software. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-11 ID073015 Non-Confidential...

  • Page 23: Product Revisions

    Optimized accesses to the L2 memory interface on page 8-7. • Change to the serializing behavior of . See Serializing instructions on page B-9. • ID Register values changed to reflect correct revision. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-12 ID073015 Non-Confidential...
  • Page 24 Addition of new hardware configuration options for the TLB, BTAC, GHB and Instruction micro TLB sizes. See Configurable options on page 1-8. • Enhanced data prefetching mechanism. See Data prefetching on page 7-11 r4p0-r4p1 No change. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 1-13 ID073015 Non-Confidential...
  • Page 25 About the functions on page 2-2 • Interfaces on page 2-4 • Clocking and resets on page 2-6 • Power management on page 2-10 • Constraints and limitations of use on page 2-15. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 26: Chapter 2 Functional Description

    Functional Description About the functions The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. Figure 2-1 shows a top-level diagram of the Cortex-A9 processor. Cortex-A9 processor Program Trace Performance...
  • Page 27 Functional Description The scheme maps the 32 ARM architectural registers to a pool of 56 physical 32-bit registers, and renames the flags (N, Z, C, V, Q, and GE) of the CPSR using a dedicated pool of eight physical 9-bit registers.

  • Page 28: Interfaces

    CoreSight PTM-A9 Technical Reference Manual for more information. Trace must be disabled in some regions. The prohibited regions are described in the ARM Architecture Reference Manual. The Cortex-A9 processor must determine prohibited regions for non-invasive debug in regions, including trace, performance monitoring, and PC sampling.
  • Page 29 Functional Description Note Only entry to and exit from Jazelle state are traced. A waypoint to enter Jazelle state is followed by a waypoint to exit Jazelle state. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 30: Clocking And Resets

    Cortex-A9 processor reset. nDBGRESET The nDBGRESET signal is the reset that initializes the debug logic. See Chapter 10 Debug. All of these are active-LOW signals. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 31 Power-on reset with the only difference that nDBGRESET must remain HIGH during the sequence, to ensure that all values in the debug registers are maintained. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 32 SIMD MPE logic is implemented in its own dedicated power domain, separated from the rest of the processor logic. ARM recommends the following reset sequence for an MPE SIMD reset: Apply nNEONRESET. Wait for at least nine CLK cycles. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by for example applying 15 cycles on every clock domain.
  • Page 33 When dynamic clock gating is enabled, the clock of the data engine is cut when there is no data engine instruction in the data engine and no data engine instruction in the pipeline. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 34: Power Management

    No clock Run Mode with Powered-up Powered-up Powered off The MPE can be implemented in a separate power MPE powered off domain and be powered off separately Clocked ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-10 ID073015 Non-Confidential...
  • Page 35 The debug request can be generated by an externally generated debug request, using the EDBGRQ pin on the Cortex-A9 processor, or from a Debug Halt instruction issued to the Cortex-A9 processor through the APB debug port. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-11 ID073015 Non-Confidential...
  • Page 36 RAMs that remain powered up in dormant mode, must be saved to external memory. These state saving operations must ensure that the following occur: • All ARM registers, including CPSR and SPSR registers are saved. • All system registers are saved.
  • Page 37 The Cortex-A9 processor can have the following power domains: • Cortex-A9 processor logic cells • Cortex-A9 processor data engines • Cortex-A9 processor RAMs. Figure 2-4 on page 2-14 shows the power domains. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-13 ID073015 Non-Confidential...
  • Page 38 There is static and dynamic high-level clock-gating. When NEON is present, you can run FPU (non-SIMD) code without powering the SIMD part or clocking the SIMD part. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-14 ID073015 Non-Confidential...

  • Page 39: Constraints And Limitations Of Use

    Note When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 2-15 ID073015 Non-Confidential...
  • Page 40 Multiprocessing Extensions on page 3-7 • Modes of operation and execution on page 3-8 • Memory model on page 3-9 • Addresses in the Cortex-A9 processor on page 3-10. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 41: Chapter 3 Programmers Model

    Programmers Model About the programmers model The Cortex-A9 processor implements the ARMv7-A architecture. See the ARM Architecture Reference Manual for information about the ARMv7-A architecture. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 42: Thumbee Architecture

    Programmers Model ThumbEE architecture The Thumb Execution Environment (ThumbEE) extension is a variant of the Thumb instruction set that is designed as a target for dynamically generated code. See the ARM Architecture Reference Manual for more information. ARM DDI 0388I Copyright ©...

  • Page 43: The Jazelle Extension

    The Jazelle Extension The Cortex-A9 processor provides hardware support for the Jazelle Extension. The processor accelerates the execution of most bytecodes. Some bytecodes are executed by software routines. See the ARM Architecture Reference Manual for more information. Chapter 5 Jazelle DBX registers.

  • Page 44: Advanced Simd Architecture

    The Advanced SIMD architecture extension, its associated implementations, and supporting software, are commonly referred to as NEON MPE. NEON MPE includes both Advanced SIMD instructions and the ARM VFPv3 instructions. All Advanced SIMD instructions and VFP instructions are available in both ARM and Thumb states.

  • Page 45: Security Extensions Architecture

    Security Extensions enable the construction of a secure software environment. This section describes the following: • System boot sequence. See the ARM Architecture Reference Manual for more information. 3.5.1 System boot sequence Caution The Security Extensions enable the construction of an isolated software environment for more secure execution, depending on a suitable system design around the processor.

  • Page 46: Multiprocessing Extensions

    Programmers Model Multiprocessing Extensions The Multiprocessing Extensions are a set of features that enhance multiprocessing functionality. See the ARM Architecture Reference Manual for more information. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 47: Modes Of Operation And Execution

    Thumb Jazelle ThumbEE Note Transition between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual for information on entering and exiting ThumbEE state. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.

  • Page 48: Memory Model

    The processor can store words in memory in either big-endian format or little-endian format. Instructions are always treated as little-endian. Note ARMv7 does not support the BE-32 memory model. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 49: Addresses In The Cortex-A9 Processor

    Secure, even if the first level descriptor is marked as NS. Note Secure L2 lookups are secure even if the L1 entry is marked Non-secure. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 3-10 ID073015 Non-Confidential...

  • Page 50: System Control

    This chapter describes the system control registers, their structure, operation, and how to use them. It contains the following sections: • About system control on page 4-2 • Register summary on page 4-3 • Register descriptions on page 4-18. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 51: About System Control

    • Wait for Interrupt. The use of the registers is optional and deprecated. In addition, the Fast Context Switch Extensions are deprecated in ARM v7 architecture, and are not implemented in the Cortex-A9 processor. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.

  • Page 52: Register Summary

    This section gives a summary of the CP15 system control registers. For more information on using the CP15 system control registers, see the ARM Architecture Reference Manual. The system control coprocessor is a set of registers that you can write to and read from. Some of these registers support more than one type of operation.
  • Page 53 Operational register number within CRn Opcode_2 value for the register Name Short form architectural, operation, or code name for the register Reset Reset value of register Description Cross-reference to register description ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 54 0x09000003 AIDR Auxiliary ID Register on page 4-23 0x00000000 CSSELR Cache Size Selection Register on page 4-24 a. Depends on TLBSIZE. See TLB Type Register on page 4-19. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 55 Table 4-5 shows the CP15 system control registers you can access when CRn is c3. Table 4-5 c3 register summary Name Type Reset Description DACR Domain Access Control Register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 56 CP15 system control registers you can access when CRn is c6. Table 4-7 c6 register summary Name Type Reset Description DFAR Data Fault Address Register IFAR Instruction Fault Address Register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 57 DCCSW User Deprecated registers on page 4-2 User DCCVAU Cache operations registers DCCIMVAC DCCISW a. This operation is performed by the instruction. See Deprecated registers on page 4-2. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 58 Event Count Registers PMUSERENR User Enable Register 0x00000000 PMINTENSET Interrupt Enable Set Register 0x00000000 PMINTENCLR Interrupt Enable Clear Register 0x00000000 a. RO in User mode. Chapter 11 Performance Monitoring Unit. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 59 Virtualization Interrupt Register Virtualization Interrupt Register on page 4-40 0x00000000 a. Only the secure version is reset to 0. The Non-secure version must be programmed by software. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-10 ID073015 Non-Confidential...
  • Page 60 In Cortex-A9 MPCore implementations the configuration base address is reset to PERIPHBASE[31:13] so that software can determine the location of the private memory region. e. No access in Non-secure state. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-11 ID073015 Non-Confidential...
  • Page 61 Cache Size Selection Register on page 4-24 a. Depends on TLBSIZE. See TLB Type Register on page 4-19. See the ARM Architecture Reference Manual for more information on the Processor ID Registers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.
  • Page 62 Auxiliary Instruction Fault Status Register DFAR Data Fault Address Register IFAR Instruction Fault Address Register 4.2.20 Other system control registers Table 4-19 on page 4-14 shows the other system control registers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-13 ID073015 Non-Confidential...
  • Page 63 DCCVAC DCCSW DCCVAU DCCIMVAC DCCISW 4.2.22 Address translation operations Table 4-21 shows the address translation register and operations. Table 4-21 Address translation operations Name Type Reset Description ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-14 ID073015 Non-Confidential...
  • Page 64 Event Type Selection Register PMXEVCNTR Event Count Registers PMUSERENR User Enable Register 0x00000000 PMINTENSET Interrupt Enable Set Register 0x00000000 PMINTENCLR Interrupt Enable Clear Register 0x00000000 a. RO in User mode. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-15 ID073015 Non-Confidential...
  • Page 65 Preload Engine User Accessibility Register on page 4-38 User RO PLEPCR Privileged R/W Preload Engine Parameters Control Register on page 4-39 User RO a. RAZ if the PLE is not present. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-16 ID073015 Non-Confidential...
  • Page 66 In Cortex-A9 uniprocessor implementations the Configuration Base Address is set to zero. In Cortex-A9 MPCore implementations the Configuration Base Address is reset to PERIPHBASE[31:13] so that software can determine the location of the private memory region. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-17 ID073015 Non-Confidential...

  • Page 67: Register Descriptions

    System Control Register descriptions This section describes the implementation-defined CP15 system control registers by coprocessor register number order that are not already described in the ARM Architecture Reference Manual. 4.3.1 Main ID Register The MIDR characteristics are: Purpose Provides identification information for the processor, including an implementer code for the device and a device ID number.
  • Page 68 MRC p15,0,<Rd>,c0,c0,3; returns TLB details 4.3.3 Multiprocessor Affinity Register The MPIDR characteristics are: Purpose To identify: • whether the processor is part of a Cortex-A9 MPCore implementation ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-19 ID073015 Non-Confidential...
  • Page 69 In the uniprocessor version this value is fixed at a. A uniprocessor implementation does not include any CLUSTERID pins. To access the MPIDR, read the CP15 register with: MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-20 ID073015 Non-Confidential...
  • Page 70 Secure and Non-secure states. Configurations Available in all configurations. Attributes See the register summary in Table 4-2 on page 4-5. Figure 4-5 on page 4-22 shows the CCSIDR bit assignments. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-21 ID073015 Non-Confidential...
  • Page 71 Selection Register on page 4-24. 4.3.6 Cache Level ID Register The CLIDR characteristics are: Purpose Identifies: • the type of cache, or caches, implemented at each level ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-22 ID073015 Non-Confidential...
  • Page 72 The AIDR characteristics are: Purpose Provides implementation-specific information. Usage constraints The AIDR is: • only accessible in privileged modes • common to the Secure and Non-secure states. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-23 ID073015 Non-Confidential...
  • Page 73 Data cache Instruction cache. To access the CSSELR, read the CP15 register with: MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELRMCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-24 ID073015 Non-Confidential...
  • Page 74 Function [31] SBZ. [30] Banked Thumb exception enable: Exceptions, including reset, are handled in ARM state Exceptions, including reset, are handled in Thumb state. The TEINIT signal defines the reset value. [29] Banked Access Flag enable bit: Full access permissions behavior. This is the reset value.
  • Page 75 Program flow prediction enabled. [10] SW bit Banked SWP/SWPB enable bit: SWP and SWPB are .This is the reset value. UNDEFINED SWP and SWPB perform normally. [9:7] RAZ/SBZP. [6:3] RAO/SBOP. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-26 ID073015 Non-Confidential...
  • Page 76 Only accessible in privileged modes. • Common to the Secure and Non-secure states. • RW in Secure state. • RO in Non-secure state if NSACR.NS_SMP = 0. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-27 ID073015 Non-Confidential...
  • Page 77 If parity checking is not implemented this bit reads as zero and writes are ignored. Alloc in one Enable allocation in one cache way only. For use with memory copy operations to reduce cache pollution. The reset value is zero. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-28 ID073015 Non-Confidential...
  • Page 78 Note This register has no effect on access to CP14 or CP15. Usage constraints The CPACR is: • only accessible in privileged modes ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-29 ID073015 Non-Confidential...
  • Page 79 Access denied. This is the reset value. Attempted access generates an Undefined Instruction exception. Privileged mode access only. Reserved. Privileged and User mode access. [19:0] RAZ/WI. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-30 ID073015 Non-Confidential...
  • Page 80 MCR p15, 0,<Rd>, c1, c0, 2; Write Coprocessor Access Control Register You must execute an immediately after an update of the CPACR. See the ARM Architecture Reference Manual for more information. You must not attempt to execute any instructions that are affected by the change of access rights between the and the register update.
  • Page 81 NSACR bit assignments. 19 18 17 16 14 13 12 11 10 9 UNK/SBZP UNK/SBZP NS_SMP NSASEDIS NSD32DIS UNK/SBZP CP11 CP10 Figure 4-12 NSACR bit assignments ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-32 ID073015 Non-Confidential...
  • Page 82 MCR p15, 0,<Rd>, c1, c1, 2; Write NSACR data See the Cortex-A9 Floating-Point Unit Technical Reference Manual and Cortex-A9 NEON Media Processing Engine Technical Reference Manual for more information. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-33 ID073015 Non-Confidential...
  • Page 83 To access the VCR, read or write the CP15 register with: MRC p15, 0,<Rd>, c1, c1, 3; Read VCR data MCR p15, 0,<Rd>, c1, c1, 3; Write VCR data ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-34 ID073015 Non-Confidential...
  • Page 84 0 to 3. Means subsequent hardware translation table walks place the TLB entry in the set-associative region of the TLB. Invalidate TLB Entries on ASID Match on page 4-45. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-35 ID073015 Non-Confidential...
  • Page 85 • accessible in User and privileged modes, regardless of any configuration bit. Configurations Available in all Cortex-A9 configurations regardless of whether a PLE is present or not. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-36 ID073015 Non-Confidential...
  • Page 86 Available in all Cortex-A9 configurations regardless of whether a PLE is present or not. Attributes Table 4-12 on page 4-10. Figure 4-17 shows the PLEFSR bit assignments. Available RAZ/WI entries Figure 4-17 PLESFR bit assignments ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-37 ID073015 Non-Confidential...
  • Page 87 To access the PLEUAR, read or write the CP15 register with: MCR p15, 0, <Rt>, c11, c1, 0; Read PLEAUR MRC p15, 0, <Rt>, c11, c1, 0; Write PLEAUR ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-38 ID073015 Non-Confidential...
  • Page 88 When PLE wait states is 8’b000000000, the PLE engine can issue one PLD request every cycle. To access the PLEPCR, read or write the CP15 register with: ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-39 ID073015 Non-Confidential...
  • Page 89 To access the VIR, read or write the CP15 register with: MRC p15, 0, <Rd>, c12, c1, 1 ; Read Virtualization Interrupt Register MCR p15, 0, <Rd>, c12, c1, 1 ; Write Virtualization Interrupt Register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-40 ID073015 Non-Confidential...

  • Page 90: Power Control Register

    Samples the value present on the MAXCLKLATENCY pins on exit from reset. This value reflects an implementation-specific parameter. ARM strongly recommends that the software does not modify it. The max_clk_latency bits determine the length of the delay between when one of these blocks has its clock cut and the time when it can receive new active signals.
  • Page 91 Attributes See the register summary in Table 4-15 on page 4-11. Figure 4-23 on page 4-43 shows the Configuration Base Address Register bit assignments. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-42 ID073015 Non-Confidential...
  • Page 92 Figure 4-24 Lockdown TLB index bit assignments Figure 4-25 shows the bit arrangement of the TLB VA Register format. 11 10 9 Process UNK/SBZP Figure 4-25 TLB VA Register bit assignments ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-43 ID073015 Non-Confidential...
  • Page 93 Bits of the physical page number that are not translated as part of the page table translation are UNPREDICTABLE when read and SBZP when written. [11:8] UNK/SBZP. [7:6] Region Size: 16MB Supersection 4KB page 64KB page 1MB section. All other values are reserved. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 4-44 ID073015 Non-Confidential...
  • Page 94 Domain Domain number of the TLB entry. Execute Never attribute. [5:3] Region type encoding. See the ARM Architecture Reference Manual. [2:1] Shared attribute. Invalidate TLB Entries on ASID Match This is a single operation that invalidates all TLB entries that match the provided Address Space Identifier (ASID) value.
  • Page 95 This chapter introduces the CP14 coprocessor and describes the non-debug use of CP14. It contains the following sections: • About coprocessor CP14 on page 5-2 • CP14 Jazelle register summary on page 5-3 • CP14 Jazelle register descriptions on page 5-4. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 96: About Coprocessor Cp14

    Jazelle DBX registers About coprocessor CP14 The non-debug use of coprocessor CP14 provides support for the hardware acceleration of Java bytecodes. See the ARM Architecture Reference Manual for more information. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015...

  • Page 97: Cp14 Jazelle Register Summary

    See Write operation of the JIDR on page 5-5 for the effect of a write operation. See the ARM Architecture Reference Manual for information about the Jazelle Extension. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015...

  • Page 98: Cp14 Jazelle Register Descriptions

    Indicates the size of the Jazelle Configurable Opcode Translation Table Register. To access the JIDR, read the CP14 register with: MRC p14, 7, <Rd>, c0, c0, 0; Read Jazelle Identity Register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 99 1 = Jazelle configuration from User mode is disabled: • reading any Jazelle configuration register generates an Undefined Instruction exception • writing any Jazelle configuration register generates an Undefined Instruction exception. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 100 The Object Pointer (OP) bit controls how the Jazelle hardware treats object references on the operand stack: Object references are treated as handles. Object references are treated as pointers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 101 Table 5-1 on page 5-3. Figure 5-4 shows the Jazelle Parameters Register bit assignments. 22 21 17 16 12 11 UNK/SBZP sADO Figure 5-4 Jazelle Parameters Register bit assignments ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 102 Figure 5-5 Jazelle Configurable Opcode Translation Table Register bit assignments Table 5-6 shows the Jazelle Configurable Opcode Translation Table Register bit assignments. Table 5-6 Jazelle Configurable Opcode Translation Table Register bit assignments Bits Name Function [31:16] UNK/SBZP ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 103 To access the Jazelle Configurable Opcode Translation Table Register, write the CP14 register with: MCR p14, 7, <Rd>, c4, c0, 0; Write Jazelle Configurable Opcode Translation Table Register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 104 About the MMU on page 6-2 • TLB Organization on page 6-4 • Memory access sequence on page 6-6 • MMU enabling or disabling on page 6-7 • External aborts on page 6-8. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 105: Chapter 6 Memory Management Unit

    • extended permissions check capability. See the ARM Architecture Reference Manual for a full architectural description of the VMSAv7. The processor implements the ARMv7-A MMU enhanced with Security Extensions and multiprocessor extensions to provide address translation and access permission checks. The MMU controls table walk hardware that accesses translation tables in main memory.

  • Page 106: System Control Coprocessor

    TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated within the processor. This coprocessor provides a standard mechanism for configuring the level one memory system. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 107: Tlb Organization

    TLB. If no mapping for an address is found in the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 108 Memory Management Unit TLB lockdown The TLB supports the TLB lock-by-entry model as described in the ARM Architecture Reference Manual. See TLB lockdown operations on page 4-43 for more information. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.

  • Page 109: Memory Access Sequence

    MMU signals a memory abort. See the ARM Architecture Reference Manual for a description of access permission bits, abort types and priorities, and for a description of the IFSR and Data Fault Status Register (DFSR).

  • Page 110: Mmu Enabling Or Disabling

    Memory Management Unit MMU enabling or disabling You can enable or disable the MMU as described in the ARM Architecture Reference Manual. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 111: External Aborts

    To determine a fault type, read the DFSR for a data abort or the IFSR for an instruction abort. The processor supports an Auxiliary Fault Status Register for software compatibility reasons only. The processor does not modify this register because of any generated abort. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 112 About the L1 data side memory system on page 7-8 • About DSB on page 7-10 • Data prefetching on page 7-11 • Parity error support on page 7-12. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 113: Chapter 7 Level 1 Memory System

    The instruction cache has the following features: • The instruction cache is virtually indexed and physically tagged. • Instruction cache replacement policy is either pseudo round-robin or pseudo random. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 114 Store buffer The Cortex-A9 processor has a store buffer with four 64-bit slots with data merging capability. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 115: Security Extensions Support

    Level 1 Memory System Security Extensions support The Cortex-A9 processor supports the Security Extensions, and exports the Secure or Non-secure status of its memory requests to the memory system. See the ARM Architecture Reference Manual for more information. ARM DDI 0388I Copyright ©...

  • Page 116: About The L1 Instruction Side Memory System

    The prediction scheme is available in ARM state, Thumb state, ThumbEE state, and Jazelle state. It is also capable of predicting state changes from ARM to Thumb, and from Thumb to ARM. It does not predict — any other state changes —...
  • Page 117 Predicted and nonpredicted instructions This section shows the instructions that the processor predicts. Unless otherwise specified, the list applies to ARM, Thumb, ThumbEE, and Jazelle instructions.As a general rule, the flow prediction hardware predicts all branch instructions regardless of the addressing mode, including: •...
  • Page 118 Because return-from-exception instructions can change processor privilege mode and security state, they are not predicted. This includes the instruction, and the LDM(3) MOVS pc, r14 instruction. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 119: About The L1 Data Side Memory System

    See Table 10-8 on page 10-11. See the ARM Architecture Reference Manual for more information about these instructions. Treatment of intervening STR operations In cases where there is an intervening operation in an...
  • Page 120 They do not reflect how the Cortex-A9 processor interprets them, and whether the access was treated as Cacheable or not. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 121: About Dsb

    The Cortex-A9 processor only implements the SY option of the instruction. All other DSB options execute as a full system DSB operation, but software must not rely on this operation. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-10 ID073015 Non-Confidential...

  • Page 122: Data Prefetching

    Requests from PLD instructions always take precedence over requests from the data prefetch mechanism. Prefetched lines in the speculative prefetcher can be dropped before they are allocated. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-11 ID073015 Non-Confidential...

  • Page 123: Parity Error Support

    Corruption in GHB data or BTAC data does not generate functional errors in the Cortex-A9 processor. Corruption in GHB data or BTAC data results in a branch misprediction, that is detected and corrected. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-12 ID073015 Non-Confidential...
  • Page 124 Level 1 Memory System Note The Cortex-A9 does not provide parity error detection support on the GHB RAMs, for GHB configurations of 8192 and 16384 entries. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 7-13 ID073015 Non-Confidential...
  • Page 125 This chapter describes the L2 memory interface. It contains the following sections: • About the Cortex-A9 L2 interface on page 8-2 • Optimized accesses to the L2 memory interface on page 8-7 • STRT instructions on page 8-9. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 126: About The Cortex-A9 L2 Interface

    Table 8-2 AXI master 1 interface attributes Attribute Format Write issuing capability None Read issuing capability 4 instruction reads Combined issuing capability Write ID capability None Write interleave capability None ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 127 Table 8-1 on page 8-2 Table 8-2 on page 8-2 are the theoretical maximums for the Cortex-A9 MPCore processor. A typical system is unlikely to reach these numbers. ARM recommends that you perform profiling to tailor your system resources appropriately for optimum performance.
  • Page 128 Write-Back Write-Allocate. b1111 Shared bit Nonshared Shared. Instruction side read bus, ARUSERM1[6:0] Table 8-4 shows the bit encodings for ARUSERM1[6:0]. Table 8-4 ARUSERM1[6:0] encodings Bits Name Description Reserved ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 129 Cortex-A9 processor. When exclusive cache configuration is selected: • Data cache line replacement policy is modified so that the victim line always gets evicted to L2 memory, even if it is clean. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 130 If a line is dirty in the L2 cache controller, a read request to this address from the processor causes writeback to external memory and a linefill to the processor. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 131: Optimized Accesses To The L2 Memory Interface

    Note You must program the L2 cache controller to benefit from this optimization. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 132 Cortex-A9 processor, to support this feature. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual. 8.2.4 Speculative coherent requests This optimization is available for Cortex-A9 MPCore processors only. See the Cortex-A9 MPCore TRM. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 133: Strt Instructions

    User Noncacheable read access User Privileged Privileged Cacheable write access Always marked as Privileged User Noncacheable write access User Privileged Noncacheable write access Privileged, except when using STRT ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 134 L2 interface. This chapter describes the PLE. It contains the following sections: • About the Preload Engine on page 9-2 • PLE control register descriptions on page 9-3 • PLE operations on page 9-4. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 135: Chapter 9 Preload Engine

    The number of entries in the FIFO can be set as an RTL configuration design choice. Available sizes are: • 16 entries • 8 entries • 4 entries. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 136: Ple Control Register Descriptions

    Preload Engine Parameters Control Register on page 4-39. For all CP15 c11 system control registers, NSAC.PLE controls Non-secure accesses. operations on page 9-4 shows the operations to use with these control registers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 137: Ple Operations

    If you perform a PLERC operation when the PLE is not paused, the Resume Channel operation is ignored. To perform a PLERC operation, use: MCR p15, 0, <Rt>, c11, c3, 1 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 138 Values range from 8’b00000000, indicating a single block preload, to 8’b11111111 indicating 256 blocks. [1:0] RAZ/WI To program a new channel operation, use the MCRR operation: MCRR p15, 0, <Rt>,<Rt2> c11; Program new PLE channel ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 139 In cases of FIFO overflow, the instruction silently fails, and the FIFO Overflow event signal is asserted. See Preload events in Table 11-6 on page 11-8. See PLE FIFO Status Register on page 4-37. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 140: Debug

    • Debug register descriptions on page 10-7 • Debug management registers on page 10-13 • Debug events on page 10-15 • External debug interface on page 10-16. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-1 ID073015 Non-Confidential...

  • Page 141: Debug Systems

    Cortex-A9 test chip or a silicon part with a Cortex-A9 processor. The debug target must implement some system support for the protocol converter to access the processor debug unit using the Advanced Peripheral Bus (APB) slave port. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-2 ID073015 Non-Confidential...

  • Page 142: About The Cortex-A9 Debug Interface

    Debug 10.2 About the Cortex-A9 debug interface The Cortex-A9 processor implements the ARMv7 debug architecture as described in the ARM Architecture Reference Manual. In addition, there are: • Cortex-A9 processor specific events. These are described in Performance monitoring events on page 11-7.

  • Page 143: Debug Register Features

    MPE is present, have no effect on the debug logic. On a debug reset: • The debug state is unchanged. That is, DBGSCR.HALTED is unchanged. • The processor removes the pending halting debug events DBGDRCR.HaltReq. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-4 ID073015 Non-Confidential...

  • Page 144: Debug Register Summary

    — DBGTR-int. External views of DBSCR and DBGTR are accessible through memory-mapped APB access. Table 10-1 shows the CP14 interface registers. All other registers are described in the ARM Architecture Reference Manual. Table 10-1 CP14 Debug register summary Register Offset...
  • Page 145 The Extended CP14 interface instructions that map to these registers are in User mode and UNDEFINED UNPREDICTABLE privileged modes. You must use the CP15 interface to access these registers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-6 ID073015 Non-Confidential...

  • Page 146: Debug Register Descriptions

    BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are Should Be Zero or Preserved on writes and Read As Zero on reads because these registers do not support context ID comparisons. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-7 ID073015 Non-Confidential...
  • Page 147 BRP is linked to another BRP that is not configured for linked context ID matching, it is whether a breakpoint debug event is generated. UNPREDICTABLE ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-8 ID073015 Non-Confidential...
  • Page 148 Supervisor access control. The breakpoint can be conditioned on the mode of the processor: User, System, or Supervisor. Privileged. User. Any. Breakpoint enable: Breakpoint disabled, reset value. Breakpoint enabled. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-9 ID073015 Non-Confidential...
  • Page 149 WVR1 WCR1 0x184 0x1C4 WVR2 0x1C8 WCR2 0x188 WVR3 WCR3 0x18C 0x1DC A pair of watchpoint registers, WVRn and WCRn, is called a Watchpoint Register Pair (WRPn). ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-10 ID073015 Non-Confidential...
  • Page 150 If this WRP is linked to a BRP that is not configured for linked context ID matching, it is whether a watchpoint debug event is generated. UNPREDICTABLE ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-11 ID073015 Non-Confidential...
  • Page 151 A store exclusive can generate an MMU fault or cause the processor to take a data watchpoint exception regardless of the state of the local monitor. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-12 ID073015 Non-Confidential...

  • Page 152: Debug Management Registers

    Peripheral Identification Registers The Peripheral Identification Registers are read-only registers that provide standard information required by all components that conform to the ARM Debug interface v5 specification. The Peripheral Identification Registers are accessible from the Debug APB bus. Only bits [7:0] of each register are used.
  • Page 153 1019 DBGPID3 Peripheral Identification Register 3 0xFEC 0x00 See the ARM Debug Interface v5 Specification for more information on the Peripheral ID Registers. 10.6.2 Component Identification Registers The Component Identification Registers are read-only registers that provide standard information required by all components that conform to the ARM Debug interface v5 specification.

  • Page 154: Debug Events

    Cache maintenance operations do not generate watchpoint events. 10.7.2 Asynchronous aborts The Cortex-A9 processor ensures that all possible outstanding asynchronous data aborts are recognized prior to entry to debug state. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-15 ID073015 Non-Confidential...

  • Page 155: External Debug Interface

    SPIDEN is LOW, the processor is not permitted to enter Halting Debug Mode even if the SDR.SUIDEN bit is set to 1. You can bypass this restriction by setting the external SPIDEN pin HIGH. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-16 ID073015 Non-Confidential...
  • Page 156 For example, this might be a single instruction that writes certain value to a control register in a system peripheral. If step 1 involves any memory operation, issue a DSB. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-17 ID073015 Non-Confidential...
  • Page 157 Figure 10-6 on page 10-19 shows the Cortex-A9 connections specific to debug request and restart. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-18 ID073015 Non-Confidential...
  • Page 158 DBGROMADDR gives the base address for the ROM table that locates the physical addresses of the debug components. DBGSELFADDR gives the offset from the ROM table to the physical addresses of the processor registers. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 10-19 ID073015 Non-Confidential...
  • Page 159 About the Performance Monitoring Unit on page 11-2 • PMU register summary on page 11-3 • PMU management registers on page 11-5 • Performance monitoring events on page 11-7. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-1 ID073015 Non-Confidential...

  • Page 160: Chapter 11 Performance Monitoring Unit

    The Cortex-A9 PMU provides six counters to gather statistics on the operation of the processor and memory system. Each counter can count any of the 58 events available in the Cortex-A9 processor. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-2 ID073015 Non-Confidential...

  • Page 161: Pmu Register Summary

    Reserved 0x018- 0x078 PMCCNTR Cycle Count Register, see the ARM 0x07C Architecture Reference Manual 32-255 Reserved 0x080- 0x3FC PMXEVTYPER0 Event Type Selection Register, see the ARM 0x400 Architecture Reference Manual PMXEVTYPER1 0x404 PMXEVTYPER2 0x408 PMXEVTYPER3 0x40C PMXEVTYPER4 0x410 PMXEVTYPER5 0x414...
  • Page 162 Table 11-1 PMU register summary (continued) Register Offset Name Type Description number 785-791 Reserved 0xC44- 0xC5C PMINTENCLR Interrupt Enable Clear Register, see the ARM 0xC60 Architecture Reference Manual 793-799 Reserved 0xC64- 0xC7C PMOVSR Overflow Flag Status Register, see the ARM 0xC80 Architecture Reference Manual 801-807...

  • Page 163: Pmu Management Registers

    Peripheral Identification Registers The Peripheral Identification Registers are read-only registers that provide standard information required by all components that conform to the ARM Debug interface v5 specification. The Peripheral Identification Registers are accessible from the Debug APB bus. Only bits [7:0] of each register are used the remaining bits Read-As-Zero.
  • Page 164 1019 PMPID3 Peripheral Identification Register 3 0xFEC 0x00 See the ARM Debug Interface v5 Specification for more information on the Peripheral ID Registers. 11.3.2 Component Identification Registers The Component Identification Registers are read-only registers that provide standard information required by all components that conform to the ARM Debug interface v5 specification.

  • Page 165: Performance Monitoring Events

    This event is not implemented. However, similar functionality is provided by event number 0x6E, Predictable function returns. See Table 11-6 on page 11-8 For more information about these events see the ARM Architecture Reference Manual. For events and the corresponding PMUEVENT signals, see Table A-18 on page A-14.
  • Page 166 Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions. Issue is empty. Precise 0x67 Counts the number of cycles where the issue stage is empty. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-8 ID073015 Non-Confidential...
  • Page 167 The counted instructions are still speculative. Second execution unit instructions. Approximate 0x71 Counts the number of instructions being executed in the processor second execution pipeline (ALU). The counted instructions are still speculative. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-9 ID073015 Non-Confidential...
  • Page 168 Counts the number of cycles when the data engine clock is enabled. Approximate NEON SIMD clock enabled. 0x8C Counts the number of cycles when the NEON SIMD clock is enabled. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-10 ID073015 Non-Confidential...
  • Page 169 This event has no corresponding mapping on PMUEVENT. It can be counted only in the Cortex-A9 internal PMU event counters. d. Active only when the PLE is present. Otherwise reads as 0. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. 11-11 ID073015...
  • Page 170 Parity signal on page A-18 • MBIST interface on page A-19 • Scan test signal on page A-20 • External Debug interface on page A-21 • PTM interface signals on page A-24. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 171: Appendix A Signal Descriptions

    Clocking and resets on page 2-6. MAXCLKLATENCY[2:0] Implementation-specific static value Controls dynamic clock gating delays. This pin is sampled during reset of the processor. Power Control Register on page 4-41. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 172: Reset Signals

    Do not cut MPE SIMD logic clock. Cut MPE SIMD logic clock. Cortex-A9 MPE SIMD logic reset. nNEONRESET a. Only if the MPE is present. Reset on page 2-6. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 173: Interrupts

    The processor treats the nFIQ input as level sensitive. nIRQ Interrupt sources Cortex-A9 processor IRQ request input line. Active-LOW interrupt request: Activate interrupt. Do not activate interrupt. The processor treats the nIRQ input as level sensitive. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 174: Configuration Signals

    Table A-5 CP15SDISABLE signal Name Source Description CP15SDISABLE Security Disables write access to some system control processor registers in Secure state: controller Not enabled. Enabled. System Control Register on page 4-25. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 175: Wfe And Wfi Standby Signals

    Processor in WFE standby mode. STANDBYWFI Indicates if the processor is in WFI mode: Processor not in WFI standby mode. Processor in WFI standby mode. Standby modes on page 2-11. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 176: Power Management Signals

    Clamps not active. Clamps active. Activates the Cortex-A9 MPE SIMD logic clamps: NEONCLAMP Clamps not active. Clamps active. a. Only if the MPE is present. Power management on page 2-10. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 177: Axi Interfaces

    Burst type = b01, INCR incrementing burst. AWCACHEM0[3:0] Cache type giving additional information about cacheable characteristics, determined by the memory type and Outer cache policy for the memory region. AWIDM0[1:0] Request ID. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 178 Source or destination Description WDATAM0[63:0] AXI system devices Write data WIDM0[1:0] Write ID WLASTM0 Write last indication WREADYM0 Write ready WSTRBM0[7:0] Write byte lane strobe WVALIDM0 Write valid ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 179 [4:1] memory type and Inner cache policy: Strongly Ordered. b0000 Device. b0001 Normal Memory Non-Cacheable. b0011 Write-Through. b0110 Write-Back no Write-Allocate. b0111 Write-Back Write-Allocate. b1111 [0] shared. ARVALIDM0 Address valid. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-10 ID073015 Non-Confidential...
  • Page 180 Read address channel signals for AXI Master1 on page A-12 • Read data channel signals on page A-13 • AXI Master1 Clock enable signals on page A-13. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-11 ID073015 Non-Confidential...
  • Page 181 [4:1] = Inner attributes Strongly Ordered. b0000 Device. b0001 Normal Memory Non-Cacheable. b0011 Write-Through. b0110 Write-Back no Write-Allocate. b0111 Write-Back Write-Allocate. b1111 [0] = Shared. ARVALIDM1 Address valid. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-12 ID073015 Non-Confidential...
  • Page 182 Clock enable for the AXI bus that enables the AXI interface to operate at integer ratios of the controller system clock. Clocking and resets on page 2-6. Chapter 8 Level 2 Memory Interface. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-13 ID073015 Non-Confidential...

  • Page 183: Performance Monitoring Signals

    0x09 PMUEVENT[11] Exception returns 0x0A PMUEVENT[12] Write context ID 0x0B PMUEVENT[13] Software change of PC 0x0C PMUEVENT[14] Immediate branch 0x0D Unused 0x0E PMUEVENT[15] Predictable function return 0x6E ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-14 ID073015 Non-Confidential...
  • Page 184 Data main TLB miss stall 0x83 PMUEVENT[43] Instruction micro TLB miss stall 0x84 PMUEVENT[44] Data micro TLB miss stall 0x85 PMUEVENT[45] DMB stall 0x86 PMUEVENT[46] Integer core clock enabled 0x8A ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-15 ID073015 Non-Confidential...
  • Page 185 Not generated by Cortex-A9 processors. Replaced by the similar event 0x68 b. Not generated by Cortex-A9 processors. Replaced by the similar event 0x6E c. Used in multiprocessor configurations. Cortex-A9 specific events on page 11-8. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-16 ID073015 Non-Confidential...

  • Page 186: Exception Flags Signal

    Bits [4:0] give the value of FPSCR[4:0]. For additional information on the FPSCR, see the Cortex-A9 Floating-Point Unit (FPU) Technical Reference Manual and the Cortex-A9 NEON Media Processing Engine Technical Reference Manual. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-17 ID073015 Non-Confidential...

  • Page 187: Parity Signal

    Bit [3] main TLB parity error Bit [2] data outer RAM parity error Bit [1] data tag RAM parity error Bit [0] data data RAM parity error. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-18 ID073015 Non-Confidential...

  • Page 188: Mbist Interface

    Name Source/Destination Description MBISTBE[25:0] MBIST controller MBIST write enable MBISTINDATA[63:0] MBIST data in MBISTOUTDATA[63:0] MBIST data out See the Cortex-A9 MBIST TRM for a description of MBIST. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-19 ID073015 Non-Confidential...

  • Page 189: Scan Test Signal

    Signal Descriptions A.12 Scan test signal Table A-24 shows the scan test signal. Table A-24 Scan test signal Name Destination Description DFT controller Scan enable: Not enabled. Enabled. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-20 ID073015 Non-Confidential...

  • Page 190: External Debug Interface

    Not enabled. Enabled. NIDEN Non-invasive debug enable: Not enabled. Enabled. SPIDEN Secure privileged invasive debug enable: Not enabled. Enabled. SPNIDEN Secure privileged non-invasive debug enable: Not enabled. Enabled. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-21 ID073015 Non-Confidential...
  • Page 191 Causes the processor to exit from Debug state. It must be held HIGH until DBGRESTARTED is deasserted. Not enabled. Enabled. DBGRESTARTED Used with DBGRESTART to move between Debug state and Normal state. Not enabled. Enabled. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-22 ID073015 Non-Confidential...
  • Page 192 If the offset cannot be determined tie this signal LOW. DBGSELFADDRV Valid signal for DBGSELFADDR. If the offset cannot be determined tie this signal LOW. Chapter 10 Debug. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-23 ID073015 Non-Confidential...

  • Page 193: Ptm Interface Signals

    WPTFLUSH Waypoint flush signal. WPTLINK The waypoint is a branch that updates the link register. Only HIGH if WPTTYPE is a direct branch or an indirect branch. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-24 ID073015 Non-Confidential...
  • Page 194 Debug exit. b101 Invalid. b110 Invalid. b111 Debug Entry must be followed by Debug Exit. Note Debug exit does not reflect the execution of an instruction. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-25 ID073015 Non-Confidential...
  • Page 195 About system control on page 4-2 for information about Security Extensions. WPTFIFOEMPTY There are no speculative waypoints in the PTM interface FIFO. Interfaces on page 2-4. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. A-26 ID073015 Non-Confidential...
  • Page 196 Data-processing instructions on page B-3 • Load and store instructions on page B-4 • Multiplication instructions on page B-7 • Branch instructions on page B-8 • Serializing instructions on page B-9. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 197: Appendix B Cycle Timings And Interlock Behavior

    Detailed descriptions of all possible instruction interactions, and all possible events taking place in the processor, is beyond the scope of this document. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 198: Data-Processing Instructions

    UXTAB UXTAB16 UXTAH SXTB STXB16 SXTH UXTB UTXB16 UXTH UBFX SBFX MOVT MOVW RBIT REV16 REVSH not modifying mode or control bits. See Serializing instructions on page B-9. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 199: Load And Store Instructions

    LDRB ,[reg reg LSL reg] LDRB ,[reg reg ASR reg] LDRH ,[reg reg LSL reg] LDRH ,[reg reg ASR reg] LDRH ,[reg reg LSL reg] LDRH ,[reg reg ASR reg] ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 200 ,{3 registers} ,{4 registers} ,{5 registers} ,{6 registers} ,{7 registers} ,{8 registers} ,{9 registers} ,{10 registers} ,{11 registers} ,{12 registers} ,{13 registers} ,{14 registers} ,{15 registers} ,{16 registers} ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 201 ,{3 registers} ,{4 registers} ,{5 registers} ,{6 registers} ,{7 registers} ,{8 registers} ,{9 registers} ,{10 registers} ,{11 registers} ,{12 registers} ,{13 registers} ,{14 registers} ,{15 registers} ,{16 registers} ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 202: Multiplication Instructions

    3 for the first written register SMLALD SMLALDX SMLSLD SMLDLDX 4 for the second written register 4 for the first written register UMAAL 5 for the second written register ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 203: Branch Instructions

    Load instructions to the PC register are processed in the execution units as standard instructions. See Load and store instructions on page B-4. About the L1 instruction side memory system on page 7-5 for information on dynamic branch prediction. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 204: Serializing Instructions

    In the r1p0 implementation waits for all previous instructions to finish, not for all instructions to finish. The following instruction, that modifies the SPSR, is serializing: • MSR SPSR ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

  • Page 205: Appendix C Revisions

    Branch instructions on page B-8. Changed LI cache coherency to L1 data cache coherency. Cortex-A9 variants on page 1-4. Corrected Processor Feature Register 0 reset value. Table 4-29 on page 4-46. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 206 Lock Status Register (DBGLSR) on page 8-49 • Authentication Status Register (DBGAUTHSTATUS) on page 8-49 • Device Type Register (DBGDEVTYPE) on page 8-50. Corrected Table 10-1 footnotes. Table 10-1 on page 10-5. ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 207 Extended PMUEVENT bus description. Performance monitoring signals on page A-14 Added PMUSECURE and PMUPRIV. Performance monitoring signals on page A-14 Updated description of serializing behavior of Serializing instructions on page B-9 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 208 Memory model on page 3-9 3.8 Security Extensions overview renamed and moved Security Extensions architecture on page 3-6 Removed content, tables and figures from 4.1 that duplicates ARM About system control on page 4-2 Architecture Reference Manual material 4.2 Duplicates of ARM Architecture Reference Manual material removed,...
  • Page 209 Chapter 11 Performance Monitoring Unit Debug chapter, About debug systems removed Debug chapter, Debugging modes removed Duplicates of ARM Architecture Reference Manual material removed External debug interface, description of PADDRDBG[12:0] added External debug interface on page 10-16 Debug APB interface section added...
  • Page 210 Synchronous and asynchronous aborts on page 6-8 Cache features cross-reference corrected Cache features on page 7-2 Implementation information removed Return stack predictions ARM or Thumb state replaced by instruction state Return stack predictions on page 7-7 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved.
  • Page 211 From r2p0 Memory system on page 7-2 Update description of accessing the Jazelle Configurable Jazelle Configurable Opcode Translation Table Opcode Translation Table Register Register on page 5-8 revisions ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 212 Update description of performance monitoring events Performance monitoring events on page 11-7 revisions Updated description of PENABLEDBG signal Table A-26 on page A-22 revisions CoreLink Level 2 Cache Controller renamed Throughout document revisions ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...
  • Page 213 Load and store instructions on page B-4 revisions Table C-8 Differences between issue H and issue I Change Location Affects Revision number changes only. Main ID Register on page 4-18 r4p1 ARM DDI 0388I Copyright © 2008-2012 ARM. All rights reserved. ID073015 Non-Confidential...

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