Debug Registers; Table 13-1 Terms Used In Register Descriptions; Table 13-2 Cp14 Debug Register Map - ARM ARM1176JZF-S Technical Reference Manual

13.3

Debug registers

Term
R
W
RW
C
UNP/SBZP
Core view
External view
Read/write
attributes
13.3.1 Accessing debug registers
ARM DDI 0301H
ID012310
Table 13-1 lists definitions of terms used in register descriptions.
Description
Read-only. Written values are ignored. However, it is written as 0 or preserved by writing the same value
previously read from the same fields on the same processor.
Write-only. This bit cannot be read. Reads return an Unpredictable value.
Read or write.
Cleared on read. This bit is cleared whenever the register is read.
Unpredictable or Should Be Zero or Preserved (SBZP). A read to this bit returns an Unpredictable value.
It is written as 0 or preserved by writing the same value previously read from the same fields on the same
processor. These bits are usually reserved for future expansion.
This column defines the core access permission for a given bit.
This column defines the DBGTAP debugger view of a given bit.
This is used when the core and the DBGTAP debugger view are the same.
On a power-on reset, all the CP14 debug registers take the values indicated by the Reset value
column in the register bit field definition tables:
• Table 13-4 on page 13-8
• Table 13-6 on page 13-14
• Table 13-11 on page 13-18
• Table 13-14 on page 13-21
• Table 13-16 on page 13-21.
In these tables, - means an Undefined Reset value.
To access the CP14 debug registers you must set Opcode_1 and CRn to 0. The Opcode_2 and
CRm fields of the coprocessor instructions are used to encode the CP14 debug register number,
where the register number is
Table 13-2 lists the CP14 debug register map. All of these registers are also accessible as scan
chains from the DBGTAP.
Binary address
Opcode_2 CRm
b000 b0000
b000 b0001
b000 b0010-b0100
b000 b0101
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Table 13-1 Terms used in register descriptions

.
{<Opcode2>, <CRm>}
Register
CP14 debug register name
number
c0 Debug ID Register
c1 Debug Status and Control Register
c2-c4 Reserved
c5 Data Transfer Register

Table 13-2 CP14 debug register map

Abbreviation
DIDR
DSCR
-
DTR
Debug
13-5