ARM ARM9TDMI Technical Reference Manual

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ARM9TDMI

Technical Reference Manual

ARM DDI0145B

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Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
Instruction interface ..................3-4 Endian effects for instruction fetches ............3-6 Data interface ....................3-7 Unidirectional/bidirectional mode interface ..........3-10 Endian effects for data transfers ............... 3-11 ARM9TDMI reset behavior ................ 3-12 ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 4 ARM9TDMI Signal Descriptions Instruction memory interface signals ............A-2 Data memory interface signals ..............A-3 Coprocessor interface signals ..............A-5 JTAG and TAP controller signals ............... A-6 Debug signals ..................... A-8 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 7 Preface This preface introduces the ARM9TDMI (Revision 1 and subsequent revisions), which is a member of the ARM family of general-purpose microprocessors. It contains the following sections: • About this document on page viii. • Further reading on page ix.
Page 8: Preface
Preface About this document This document is a reference manual for the ARM9TDMI microprocessor. The ARM9TDMI includes the following features: • The option, selectable using the UNIEN signal, of using two unidirectional buses DD[31:0] and DDIN[31:0], instead of a single bidirectional data bus. This is described in Unidirectional/bidirectional mode interface on page 3-10.
Page 9: Further Reading
Preface Further reading This section lists publications by ARM Limited, and by third parties. ARM publications ARM Architecture Reference Manual (ARM DDI 0100). ARM7TDMI Data Sheet (ARM DDI 0029). Other reading IEEE Std. 1149.1 - 1990, Standard Test Access Port and Boundary-Scan Architecture.
Page 10: Typographical Conventions
Preface Typographical conventions The following typographical conventions are used in this document: bold Highlights ARM processor signal names within text, and interface elements such as menu names. May also be used for emphasis in descriptive lists where appropriate. italic Highlights special terminology, cross-references and citations.
Page 11: Feedback
• a concise explanation of your comments. General suggestions for additions and improvements are also welcome. Feedback on the ARM9TDMI If you have any comments or suggestions about the ARM9TDMI, please contact your supplier giving: • the product name •...
Page 13: Chapter 1 Introduction
Chapter 1 Introduction This chapter introduces the ARM9TDMI (Revision 1 and subsequent revisions) and shows its processor block diagram under the headings: • About the ARM9TDMI on page 1-2. • Processor block diagram on page 1-3. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 14: About The Arm9Tdmi
The ARM9TDMI supports both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. The ARM9TDMI supports the ARM debug architecture and includes logic to assist in both hardware and software debug.
Page 15: Processor Block Diagram
Introduction Processor block diagram Figure 1-1 shows the ARM9TDMI processor block diagram. ID[..] Instruction Instruction Decode and Datapath control logic Pipeline IDScan Byte Rot DD[..] DIN[..] DINFWD[..] / Sign Ex. Cmux C[..] Byte/ DDIN[] Word Repl Shift DDScan IINC Bmux B[..]...
Page 17: Programmer's Model
Chapter 2 Programmer’s Model This chapter describes the programmer’s model for the ARM9TDMI under the headings: • About the programmer’s model on page 2-2. • Pipeline implementation and interlocks on page 2-4. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 18: About The Programmer's Model
ARM Architecture Reference Manual. The ARM v4T architecture specifies a small number of implementation options. The options selected in the ARM9TDMI implementation are listed in the table below. For comparison, the options selected for the ARM7TDMI implementation are also shown:...
Page 19 2.1.2 Instruction set extension spaces All ARM processors implement the undefined instruction space as one of the entry mechanisms for the Undefined Instruction Exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are UNDEFINED on all ARM processors including the ARM9TDMI and ARM7TDMI.
Page 20: Pipeline Implementation And Interlocks
Programmer’s Model Pipeline implementation and interlocks The ARM9TDMI implementation uses a five-stage pipeline design. These five stages are: • instruction fetch (F) • instruction decode (D) • execute (E) • data memory access (M) • register write (W). ARM implementations are fully interlocked, so that software will function identically across different implementations without concern for pipeline effects.
Page 23: Arm9Tdmi Processor Core Memory Interface
Chapter 3 ARM9TDMI Processor Core Memory Interface This chapter describes the memory interface of the ARM9TDMI processor core. The processor core has a Harvard memory architecture, and so the memory interface is separated into the instruction interface and the data interface. The information in this chapter is broken down as follows: •...
Page 24: About The Memory Interface
ARM9TDMI Processor Core Memory Interface About the memory interface The ARM9TDMI has a Harvard bus architecture with separate instruction and data interfaces. This allows concurrent instruction and data accesses, and greatly reduces the CPI of the processor. For optimal performance, single cycle memory accesses for both interfaces are required, although the core can be wait-stated for non-sequential accesses, or slower memory systems.
Page 25 Alternatively, wait states may be inserted by stretching either phase of GCLK before it is applied to the processor. ARM9TDMI does not contain any dynamic logic which relies on regular clocking to maintain its state. Therefore there is no limit on the maximum period for which GCLK may be stretched, in either phase, or the time for which nWAIT may be held LOW.
Page 26: Instruction Interface
However, in order to ease the system design, it is possible to connect the ARM9TDMI to memory which takes two (or more) cycles for a non-sequential (N) access, and one cycle for a sequential (S) access.
Page 27 Figure 3-2 shows the cycle timing for an N followed by an S cycle, where there is a prefetch abort on the S cycle: Figure 3-2 Instruction fetch timing ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 28: Endian Effects For Instruction Fetches
ITBIT signal. When this signal is LOW, the processor is in ARM state, and 32-bit instructions are fetched. When it is HIGH, the processor is in Thumb state and 16-bit instructions are fetched.
Page 29: Data Interface
If the memory control logic does not make use of the DABORT signal, it must be tied LOW, but with the exception that data can be transferred to and from the ARM9TDMI core. ARM DDI0145B...
Page 30 Reserved For coprocessor transfers, access to memory is not required, but there will be a transfer of data between the ARM9TDMI and coprocessor using the data buses, DD[31:0] and DDIN[31:0]. DnRW indicates the direction of the transfer and DMAS[1:0] indicates word transfers, as all coprocessor transfers are word sized.
Page 32: Unidirectional/Bidirectional Mode Interface
If UNIEN is LOW, DD[31:0] is a tristate output bus used to transfer write data. It is only driven when the ARM9TDMI is performing a write to memory. By wiring DD[31:0] to the input DDIN[31:0] bus (externally to the ARM9TDMI), a bidirectional data data bus can be formed.
Page 33: Endian Effects For Data Transfers
ARM9TDMI Processor Core Memory Interface Endian effects for data transfers The ARM9TDMI supports 32-bit, 16-bit and 8-bit data memory access sizes. The endian configuration of the processor, set by BIGEND, affects only non-word transfers (16-bit and 8-bit transfers). For data writes by the processor, the write data is duplicated on the data bus. So for a 16-bit data store, one copy of the data appears on the upper half of the data bus, DD[31:16], and the same data appears on the lower half, DD[15:0].
Page 34: Arm9Tdmi Reset Behavior
If GCLK is LOW, they will not change until after the GCLK goes HIGH. When nRESET is driven HIGH, the ARM9TDMI starts requesting memory again once the signal has been synchronized, and the first memory access will start two cycles later.
Page 37: Arm Ddi0145B Copyright © 1998, 1999 Arm Limited. All Rights Reserved
Chapter 4 ARM9TDMI Coprocessor Interface This chapter describes the ARM9TDMI coprocessor interface, and details the following operations: • About the coprocessor interface on page 4-2. • LDC/STC on page 4-3. • MCR/MRC on page 4-9. • Interlocked MCR on page 4-11.
Page 38: About The Coprocessor Interface
Coprocessors determine the instructions they need to execute using a pipeline follower in the coprocessor. As each instruction arrives from memory, it enters both the ARM pipeline and the coprocessor pipeline. Typically, a coprocessor operates one clock phase behind the ARM9TDMI pipeline. The...
Page 39: Ldc/Stc
The number of words transferred is determined by how the coprocessor drives the CHSD[1:0] and CHSE[1:0] buses. In the example, four words of data are transferred. Figure 4-1 on page 4-4 shows the ARM9TDMI LDC/STC cycle timing. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 41 • the fetched instruction should be latched. In all other cases, the ARM9TDMI pipeline is stalled, and the coprocessor pipeline should not advance. Figure 4-2 shows the timing for these signals, and indicates when the coprocessor pipeline should advance its state. In this timing diagram, Coproc Clock shows a processed version of GCLK with InMREQ and nWAIT.
Page 42 This is the only cycle in which LATECANCEL can be asserted. On the falling edge of the clock, the ARM9TDMI processor core examines the coprocessor handshake signals CHSD[1:0] or CHSE[1:0]: •...
Page 43 When only one further word is to be transferred, the coprocessor drives the handshake signals with LAST. In phase 2 of the execute stage, the ARM9TDMI processor core outputs the address for the LDC/STC. Also in this phase, DnMREQ is driven LOW, indicating to the memory system that a memory access is required at the data end of the device.
Page 44 ARM9TDMI Coprocessor Interface If a coprocessor is not attached to the ARM9TDMI, the handshake signals must be driven with “10” ABSENT, otherwise the ARM9TDMI processor will hang if a coprocessor enters the pipeline. If multiple coprocessors are to be attached to the interface, the handshaking signals can be combined by ANDing bit 1, and ORing bit 0.
Page 45: Mcr/Mrc
These cycles look very similar to STC/LDC. An example, with a busy-wait state, is shown in Figure 4-3: Figure 4-3 ARM9TDMI MCR / MRC transfer timing First InMREQ is driven LOW to denote that the instruction on ID is entering the decode stage of the pipeline.
Page 46 In the case of an MCR, the DD[31:0] bus is driven with the register data. In the case of an MRC, DDIN[31:0] is sampled at the end of the ARM9TDMI memory stage and written to the destination register during the next cycle.
Page 47: Interlocked Mcr
ARM9TDMI Coprocessor Interface Interlocked MCR If the data for an MCR operation is not available inside the ARM9TDMI pipeline during its first decode cycle, the ARM9TDMI pipeline will interlock for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from a preceding LDR instruction.
Page 49: Cdp
PASS. In the following phase LATECANCEL is asserted. This causes the coprocessor to terminate execution of the CDP instruction and for it to cause no state changes to the coprocessor. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 4-13...
Page 51: Privileged Instructions
InTRANS changes after a mode change. Figure 4-6 ARM9TDMI privileged instructions The first two CHSD responses are ignored by the ARM9TDMI because it is only the final CHSD response, as the instruction moves from decode into execute, that counts. This allows the coprocessor to change its response as InTRANS/InM[4:0] changes.
Page 52: Busy-Waiting And Interrupts
If it is HIGH, the instruction should still be executed. If it is LOW, the instruction should be abandoned. Figure 4-7 shows a busy-waited coprocessor instruction being abandoned due to an interrupt: Figure 4-7 ARM9TDMI busy waiting and interrupts 4-16 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 53: Coprocessor 15 Mcrs
For each cycle that the coprocessor responded with GO on the handshake signals the coprocessor data will be driven onto IA and DA as shown in Figure 4-8. Figure 4-8 ARM9TDMI coprocessor 15 MCRs ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 4-17...
Page 55: Debug Support
Chapter 5 Debug Support This chapter describes the debug support for the ARM9TDMI, including the EmbeddedICE macrocell: • About debug on page 5-2. • Debug systems on page 5-3. • Debug interface signals on page 5-5. • Scan chains and JTAG interface on page 5-11.
Page 56: About Debug
• asynchronously by a debug request. When this happens, the ARM9TDMI is said to be in debug state. At this point, the internal state of the core and the external state of the system may be examined. Once examination is complete, the core and system state may be restored and program execution resumed.
Page 57: Debug Systems
The debug host is connected to the ARM9TDMI development system via an interface (an RS232, for example). The messages broadcast over this connection must be converted to the interface signals of the ARM9TDMI. This function is performed by the protocol converter, for example, Multi-ICE.
Page 58 5.2.3 The ARM9TDMI The ARM9TDMI, with hardware extensions to ease debugging, is the lowest level of the system. The debug extensions allow the user to stall the core from program execution, examine its internal state and the state of the memory system, and then resume program execution.
Page 59: Debug Interface Signals
IEBKPT, DEWPT, and EDBGRQ, with which the system asks the ARM9TDMI to enter debug state • DBGACK, which the ARM9TDMI uses to flag back to the system when it is in debug state. 5.3.1 Entry into debug state on breakpoint Any instruction being fetched for memory is latched at the end of phase 2.
Page 60 On an instruction boundary, if there is a breakpointed instruction and an interrupt (IRQ or FIQ), the interrupt is taken and the breakpointed instruction is discarded. Once the interrupt has been serviced, the execution flow is returned to the original program. Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 61 Figure 5-4 on page 5-9. However, it is always possible to restart the processor. Once the processor has entered debug state, the ARM9TDMI core may be interrogated to determine its state. In the case of a watchpoint, the PC contains a value that is five instructions on from the address of the next instruction to be executed.
Page 64 If there is an abort with the data access as well as a watchpoint, the watchpoint condition is latched, the exception entry sequence performed, and then the processor enters debug state. If there is an interrupt pending, again the ARM9TDMI allows the exception entry sequence to occur and then enters debug state.
Page 65: Scan Chains And Jtag Interface
The signals provided for this scan chain are described on Scan chain 3 on page 5-25. The three scan chains of the ARM9TDMI are referred to as scan chain 0, 1 and 2. Note The ARM9TDMI TAP controller supports 32 scan chains.
Page 66: The Jtag State Machine
The state numbers are also shown on the diagram. These are output from the ARM9TDMI on the TAPSM[3:0] bits. Figure 5-5 Test access port (TAP) controller state transitions 5-12 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 67 In order to minimize static current draw, these resistors are not fitted to the ARM9TDMI. Accordingly, the four inputs to the test interface (the TDO, TDI and TMS signals plus TCK) must all be driven to valid logic levels to achieve normal circuit operation.
Page 68 In the SHIFT-DR state, the previously captured test data is shifted out of the scan chain via TDO, while new test data is shifted in via the TDI input. This data is applied immediately to the system logic and system pins. 5-14 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 69 ID register via the TDO pin, while data is shifted in via the TDI pin into the ID register. In the UPDATE-DR state, the ID register is unaffected. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 5-15...
Page 70 TDO after a delay of one TCK cycle. The first bit shifted out will be a zero. The bypass register is not affected in the UPDATE-DR state. HIGHZ (0111) This instruction connects a 1-bit shift register (the bypass register) between TDI and TDO. 5-16 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 71 When the HIGHZ instruction is loaded into the instruction register and scan chain 0 is selected, all ARM9TDMI outputs are driven to the high impedance state and the external HIGHZ signal is driven HIGH. This is as if the signal TBE had been driven LOW.
Page 72 TDI and TDO and the TAP controller behaves as if the BYPASS instruction had been loaded. The processor will resynchronize back to the memory system once the RUN-TEST/ IDLE state is entered. 5-18 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 73: Test Data Registers
ID register. The 32-bit identification code is loaded into the register from the parallel inputs of the TAPID[31:0] input bus during the CAPTURE-DR state. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 5-19...
Page 74 During the UPDATE-DR state, the value in the register selects a scan chain to become the currently active scan chain. All further instructions such as INTEST then apply to that scan chain. 5-20 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 75 SCREG[4:0], IR[3:0], TAPSM[3:0], TCK1 and TCK2. The list of scan chain numbers allocated by ARM are shown in Table 5-3. An external scan chain may take any other number. The serial data stream applied to the external scan chain is made present on SDIN.
Page 76 During SHIFT-DR, this captured data is shifted out while a new serial test pattern is scanned in, thus applying known values on the core’s outputs. • During RUN-TEST/IDLE, the core is not clocked. The operation may then be repeated. 5-22 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 77 • After the ARM9TDMI has entered debug state, the first time SYSSPEED is captured and scanned out, its value tells the debugger whether the core has entered debug state due to a breakpoint (SYSSPEED LOW), or a watchpoint (SYSSPEED HIGH).
Page 78 EmbeddedICE macrocell register to be accessed. During UPDATE-DR, this register is either read or written depending on the value of bit 37 (0 = read). 5-24 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 79 Scan chain 3 is provided so that an optional external boundary scan chain may be controlled via the ARM9TDMI. Typically this would be used for a scan chain around the pad ring of a packaged device. The following control signals are provided and are generated only when scan chain 3 has been selected.
Page 80: Arm9Tdmi Core Clocks
DCLK. During normal operation, the core is clocked by GCLK, and internal logic holds DCLK LOW. When the ARM9TDMI is in the debug state, the core is clocked by DCLK under control of the TAP state machine, and GCLK may free run.
Page 81: Clock Switching During Debug
Debug Support Clock switching during debug When the ARM9TDMI enters debug state, it must switch from GCLK to DCLK. This is handled automatically by logic in the ARM9TDMI. On entry to debug state, the ARM9TDMI asserts DBGACK in the HIGH phase of GCLK. The switch between the two clocks occurs on the next falling edge of GCLK.
Page 82: Clock Switching During Test
On the way into test, GCLK must be held LOW. The TAP controller can now be used to perform serial testing on the ARM9TDMI. If scan chain 0 and INTEST are selected, DCLK is generated while the state machine is in RUN-TEST/IDLE state.
Page 83: Determining The Core State And System State
If the processor has entered debug state from Thumb state, the simplest course of action is for the debugger to force the core back into ARM state. Once this is done, the debugger can always execute the same sequence of instructions to determine the processor state.
Page 84 Executing instructions more slowly than usual is fine for accessing the core’s state since the ARM9TDMI is fully static. However, this same method cannot be used for determining the state of the rest of the system.
Page 85 SYSCOMP (bit 3 of the Debug status register). To access memory, the ARM9TDMI must access memory through the data data bus interface, as this access may be stalled indefinitely by nWAIT. Therefore, the only way to determine whether the memory access has completed is to examine the SYSCOMP bit.
Page 86: Exit From Debug State
Then, when RUN-TEST/IDLE state is entered, all the processors resume operation simultaneously. The function of DBGACK is to tell the rest of the system when the ARM9TDMI is in debug state. This can be used to inhibit peripherals such as watchdog timers that have real time characteristics.
Page 89: The Behavior Of The Program Counter During Debug
5.12 The behavior of the program counter during debug To force the ARM9TDMI to branch back to the place at which program flow was interrupted by debug, the debugger must keep track of what happens to the PC. There are six cases: •...
Page 90 A similar sequence is followed when an interrupt, or any other exception, occurs during a watchpointed memory access. The ARM9TDMI will enter debug state in the mode of the exception, and so the debugger must check to see whether this happened. The debugger can deduce whether an exception occurred by looking at the current and previous mode, (in the CPSR and SPSR), and the value of the PC.
Page 91 If an abort occurs during a system speed memory access, the ARM9TDMI enters abort mode before returning to debug state. This is similar to an aborted watchpoint. However, the problem is much harder to fix because the abort was not caused by an instruction in the main program, and the PC does not point to the instruction that caused the abort.
Page 92: Embeddedice Macrocell
Debug Support 5.13 EmbeddedICE macrocell The EmbeddedICE macrocell is integral to the ARM9TDMI processor core. It has two hardware breakpoint/watchpoint units each of which may be configured to monitor either the instruction memory interface or the data memory interface. Each watchpoint unit has a value and mask register, with an address, data and control field.
Page 93 Debug Support Table 5-4 ARM9TDMI EmbeddedICE macrocell register map (continued) Address Width Function 01000 Watchpoint 0 address value 01001 Watchpoint 0 address mask 01010 Watchpoint 0 data value 01011 Watchpoint 0 data mask 01100 Watchpoint 0 control value 01101 Watchpoint 0 control mask...
Page 94 For each value register there is an associated mask register in the same format. Setting a bit to 1 in the mask register causes the corresponding bit in the value register to be ignored in any comparison. 5-40 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 95 Is an external input into the EmbeddedICE macrocell that allows the watchpoint to be dependent upon some external condition. The EXTERN input for watchpoint 0 is labelled EXTERN0, and the EXTERN input for watchpoint 1 is labelled EXTERN1. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 5-41...
Page 96 “breakpoint on address YYY only when in process XXX”. In the ARM9TDMI EmbeddedICE macrocell, the CHAINOUT output of watchpoint 1 is connected to the CHAIN input of watchpoint 0. The CHAINOUT output is derived from a latch. The address/control field comparator drives the write enable for the latch and the input to the latch is the value of the data field comparator.
Page 97 ITBIT Compares against the Thumb state signal from the core to determine between a Thumb (ITBIT = 1) instruction fetch or an ARM (ITBIT = 0) fetch. InTRANS Compares against the not translate signal from the core in order to determine between a user mode (InTRANS = 0) instruction fetch, and a privileged mode (InTRANS = 1) fetch.
Page 98 Debug Support 5.13.4 Debug control register The ARM9TDMI debug control register is four bits wide and is shown in Figure 5-12: Figure 5-12 Debug control register Bit 3 controls the single-step hardware, and this is explained in more detail in Figure 5-15 on page 5-48.
Page 99 5.13.6 Vector catch register The ARM9TDMI EmbeddedICE macrocell controls logic to enable accesses to the exception vectors to be trapped in an efficient manner. This is controlled by the vector catch register, as shown in Figure 5-14. The functionality is described in Vector catching on page 5-46.
Page 100: Vector Catching
For example, if the processor executes a SWI instruction while bit 2 of the Vector catch register is set, the ARM9TDMI fetches an instruction from location 0x8. The vector catch hardware detects this access and forces the internal Breakpoint signal HIGH into the ARM9TDMI control logic.
Page 101: Single Stepping
Debug Support 5.15 Single stepping The ARM9TDMI EmbeddedICE macrocell contains logic that allows efficient single stepping through code. This leaves the macrocell watchpoint comparators free for general use. This function is enabled by setting bit 3 of the debug control register. The state of this bit should only be altered while the processor is in debug state.
Page 102: Debug Communications Channel
Debug Support 5.16 Debug communications channel The ARM9TDMI EmbeddedICE macrocell contains a communication channel for passing information between the target and the host debugger. This is implemented as coprocessor 14. The communications channel consists of a 32-bit wide comms data read register, a 32-bit wide comms data write register and a 6-bit wide comms control register for synchronized handshaking between the processor and the asynchronous debugger.
Page 103 MRC p14, 0, Rd, C1, C0 Returns the debug data read register into Rd. Note The Thumb instruction set does not support coprocessors so the ARM9TDMI must be operated in ARM state in order to access the debug comms channel. 5.16.2...
Page 104 W bit. At this point, the communications process may begin again. As an alternative to polling, the debug comms channel can be interrupt driven by connecting the ARM9TDMI COMMRX and COMMTX signals to the systems interrupt controller. Receiving a message from the debugger Message transfer from the debugger to the processor is similar to sending a message to the debugger.
Page 105: Test Issues
Chapter 6 Test Issues This chapter examines the test issues for the ARM9TDMI and lists the scan chain 0 bit order under the headings: • About testing on page 6-2. • Scan chain 0 bit order on page 6-3. ARM DDI0145B...
Page 106: About Testing
About testing The ARM9TDMI processor core supports parallel and serial test methodologies. The parallel test patterns are derived from assembler ARM code programs written to achieve a high fault coverage. The ARM9TDMI processor core has a fully JTAG-compatible scan chain which intersects all the inputs and outputs.
Page 107: Scan Chain 0 Bit Order
Bidirectional DA[31] Output DA[30] Output 70:98 DA[29:1] Output DA[0] Output IA[31] Output IA[30] Output 102:129 IA[29:2] Output IA[1] Output IEBKPT Input DEWPT Input EDBGRQ Input EXTERN0 Input EXTERN1 Input ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 108 Output DMAS[0] Output PASS Output LATECANCEL Output ITBIT Output InTRANS Output DnTRANS Output nRESET Input nWAIT Input IABORT Input IABE Input DABORT Input DABE Input nFIQ Input nIRQ Input Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 109 Output InM[3] Output InM[2] Output InM[1] Output InM[0] Output DnM[4] Output DnM[3] Output DnM[2] Output DnM[1] Output DnM[0] Output DSEQ Output DMORE Output DLOCK Output ECLK Output INSTREXEC Output ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 111: Instruction Cycle Summary And Interlocks
Instruction Cycle Summary and Interlocks This chapter gives the instruction cycle times and shows the timing diagrams for interlock timing: • Instruction cycle times on page 7-2. • Interlocks on page 7-5. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 112: Instruction Cycle Times
The number of words transferred in an LDM/STM/LDC/STC Coprocessor register transfer (C-cycle) Internal cycle (I-cycle) Non-sequential cycle (N-cycle) Sequential cycle (S-cycle) Table 7-2 summarizes the ARM9TDMI instruction cycle counts and bus activity when executing the ARM instruction set. Table 7-2 Instruction cycle bus times Instruction Instruction...
Page 113 1S + 2I If any bits other than just the flags are updated (all masks other than_f) MUL, MLA 1S+(1+m)I (2+m)I All cases SMULL, UMULL, 1S+(2+m)I (3+m)I All cases SMLAL, UMLAL ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 114 The number of cycles that a multiply instruction takes to complete depends on which instruction it is, and on the value of the multiplier-operand. The multiplier-operand is the contents of the register specified by bits [8:11] of the ARM multiply instructions, or bits [2:0] of the Thumb multiply instructions.
Page 115: Interlocks
Pipeline interlocks occur when the data required for an instruction is not available due to the incomplete execution of an earlier instruction. When an interlock occurs, instruction fetches stop on the instruction memory interface of the ARM9TDMI. Four examples of this are given below.
Page 116 LDM begins its final memory fetch. The behavior of both the instruction and data memory interface are shown in Figure 7-3 on page 7-7. Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 117 Instruction Cycle Summary and Interlocks Figure 7-3 LDM interlock Example 4 In the fourth example, the following code sequence is executed: LDM R12,{R1-R3} ADD R4, R3, R1 ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 118 R3 is loaded. The behavior on the instruction and data memory interface is shown in Figure 7-4. Figure 7-4 LDM dependent interlock Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 119: Arm9Tdmi Ac Characteristics
Chapter 8 ARM9TDMI AC Characteristics This chapter gives the timing diagrams and timing parameters for the ARM9TDMI: • ARM9TDMI timing diagrams on page 8-2. • ARM9TDMI timing parameters on page 8-14. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 120: Arm9Tdmi Timing Diagrams
ARM9TDMI AC Characteristics ARM9TDMI timing diagrams Figure 8-1 ARM9TDMI instruction memory interface output timing Figure 8-2 ARM9TDMI instruction address bus enable Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 123 ARM9TDMI AC Characteristics Figure 8-5 ARM9TDMI data address bus timing Figure 8-6 ARM9TDMI data ABORT and DnMREQ timing Figure 8-7 ARM9TDMI data data bus timing ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 127 ARM9TDMI AC Characteristics Figure 8-12 ARM9TDMI external boundary scan chain output signals Figure 8-13 ARM9TDMI SDOUTBS to TDO relationship ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 128 ARM9TDMI AC Characteristics Figure 8-14 ARM9TDMI nTRST to RSTCLKBS relationship Figure 8-15 ARM9TDMI JTAG input signal timing 8-10 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 130 ARM9TDMI AC Characteristics Figure 8-17 ARM9TDMI TCK related debug output timings Figure 8-18 ARM9TDMI nTRST to DBGRQI relationship Figure 8-19 ARM9TDMI EDBGRQ to DBGRQI relationship 8-12 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 132: Arm9Tdmi Timing Parameters
DA[31:0] delay from GCLK rising Tdah DA[31:0] hold time from GCLK rising Tdbqh EDBGRQ input hold time from GCLK falling Tdbqs EDBGRQ input setup time to GCLK falling 8-14 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 133 DMAS[1:0] delay from GCLK rising Tdmsh DMAS[1:0] hold time from GCLK rising Tdnmd DnM[4:0] delay from GCLK rising Tdnmh DnM[4:0] hold time from GCLK rising Tdqen DBGRQI falling delay from DBGEN falling ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 8-15...
Page 134 Delay from IABE rising to IA[31:1]/InM[4:0]/InTRANS driven valid Tiabh IABORT hold time from GCLK falling Tiabs IABORT setup time to GCLK falling Tiabz Delay from IABE falling to IA[31:1]/InM[4:0]/InTRANS high impedance 8-16 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 135 ITBIT delay from GCLK rising Titbh ITBIT hold time from GCLK rising Titrsd InTRANS delay from GCLK rising Titrsh InTRANS hold time from GCLK rising Tltcd LATECANCEL delay from GCLK falling ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 8-17...
Page 136 TCK1/TCK2 falling from TCK changing Ttckh Minimum TCK HIGH period Ttckl Minimum TCK LOW period Ttckr TCK1/TCK2 rising from TCK changing Ttdod TDO output delay from TCK falling 8-18 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 137 TAPSM[3:0] output delay from TCK falling Ttpmh TAPSM[3:0] hold time from TCK falling Tunis UNIEN input setup time to GCLK falling Tunih UNIEN input hold time to GCLK falling ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 8-19...
Page 139: Arm9Tdmi Signal Descriptions
Appendix A ARM9TDMI Signal Descriptions This chapter lists and describes the ARM9TDMI signals: • Instruction memory interface signals on page A-2. • Data memory interface signals on page A-3. • Coprocessor interface signals on page A-5. • JTAG and TAP controller signals on page A-6.
Page 140: Instruction Memory Interface Signals
ITBIT Output Instruction Thumb Bit. When HIGH, the processor is in Thumb state. When LOW, the processor is in ARM state. Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 141: Data Memory Interface Signals
Output Data Mode. The processor mode within which the data memory access should be performed. Note that the data memory access mode may differ from the current processor mode. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 142 DSEQ Output Data Sequential Address. If HIGH at the end of phase 2, any data memory access in the next cycle is sequential from the current data memory access. Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 143: Coprocessor Interface Signals
Output Coprocessor PASS. This signal indicates that there is a coprocessor instruction in the execute stage of the pipeline, and it should be executed. For further information on the coprocessor interface refer to Chapter 4 ARM9TDMI Coprocessor Interface. ARM DDI0145B...
Page 144: Jtag And Tap Controller Signals
(or other external scan chain). It should be set up to the rising edge of TCK. When an external boundary scan chain is not connected, this input should be tied LOW. Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 145 Not Test Reset. Active-low reset signal for the boundary scan logic. This pin must be pulsed or driven LOW after power up to achieve normal device operation, in addition to the normal device reset (nRESET). ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 146: Debug Signals
ARM9TDMI. COMMTX Output Communications Channel Transmit. When HIGH, this signal denotes that the comms channel transmit buffer is empty and the ARM9TDMI can write new data to the comms channel. DBGACK Output Debug Acknowledge.
Page 147 DSEQ IA[31:0] InM[4:0] InTRANS InMREQ ISEQ ITBIT LATECANCEL PASS. Under normal operating conditions, TBE should be held HIGH at all times. If UNIEN is HIGH, this signal is ignored. ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved.
Page 148 Direction Description BIGEND Input Big-Endian Configuration. When this input is HIGH, the ARM9TDMI processor treats bytes in memory as being in big-endian format. When it is LOW, memory is treated as little-endian. ECLK Output External Clock. The clock by which the ARM9TDMI is currently being clocked. This clock will reflect any wait states applied by nWAIT, and once debug state has been entered by the debug clock.
Page 149 Input Not Wait. When a memory request cannot be processed in a single cycle, the ARM9TDMI can be made to wait for a number of GCLK cycles by driving nWAIT LOW. Internally, the inverse of nWAIT is ORed with GCLK, and must only change when GCLK is HIGH. If nWAIT is not used, it must be tied HIGH.
Page 151 CDP 4-13 aborted 3-7 abandoned 4-16 coprocessor 15 MCRs 4-17 access timings 3-8 interrupted 4-16 during busy-wait 4-16 coprocessor transfers 3-8 Copyright © 1998, 1999 ARM Limited. All rights reserved. Index-1 A R M D D I0 1 4 5 B...
Page 152 3-4 control registers 5-41 16-bit 3-6 debug control register 5-44 32-bit 3-6 nRESET 3-12 debug status register 5-44 instruction interface nWAIT 3-3 functionality 5-38 accessing data memory 3-3 Index-2 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B...
Page 153 0 bit order 6-1, 6-3 scan chain 1 5-23 scan chain 2 5-24 scan chain 3 5-25 serial test and debug 5-12 vector catching 5-46 signals ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. Index-3...

ARM ARM9TDMI Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 ARM9TDMI Processor Core Memory Interface

Chapter 4 ARM9TDMI Coprocessor Interface

Chapter 5 Debug Support

Chapter 6 Test Issues

Chapter 7 Instruction Cycle Summary and Interlocks

Chapter 8 ARM9TDMI AC Characteristics

ARM9TDMI Signal Descriptions

Appendix A ARM9TDMI Signal Descriptions

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