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ARM ARM966E-S Technical Reference Manual

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ARM966E-S
(Rev 1)
Technical Reference Manual
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A

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  • Page 1 ARM966E-S (Rev 1) Technical Reference Manual Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    About the programmer’s model ..............2-2 About the ARM9E-S programmer’s model ..........2-3 ARM966E-S CP15 registers ............... 2-4 Chapter 3 Memory Map About the ARM966E-S memory map ............3-2 Tightly-coupled SRAM address space ............3-3 Bufferable write address space ..............3-4 Chapter 4 Tightly-coupled SRAM ARM966E-S SRAM requirements ...............
  • Page 4 Enabling the ETM interface ................ 9-3 ARM966E-S trace support features ............9-4 Chapter 10 Test Support 10.1 About the ARM966E-S test methodology ..........10-2 10.2 Scan insertion and ATPG ................. 10-3 10.3 BIST of tightly-coupled SRAM ..............10-4 Copyright © 2000 ARM Limited. All rights reserved.
  • Page 5 DMA Signals ..................... A-15 Appendix B AC Parameters Timing diagrams ..................B-2 AC timing parameter definitions ..............B-12 Appendix C SRAM Stall Cycles About SRAM stall cycles ................C-2 ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 6 Contents Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 7 Table 11-1 I-SRAM access ....................... 11-4 Table 11-2 D-SRAM access ...................... 11-5 Table 11-3 Key to tables ......................11-7 Table 11-4 AHB read and unbuffered write transfer cycles ............11-7 ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 8 Miscellaneous signals ..................... A-11 Table A-6 ETM interface signals ..................... A-12 Table A-7 INTEST wrapper signals ..................A-14 Table A-8 DMA signals ......................A-15 Table B-1 AC parameters ......................B-12 viii Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 9 Back-to-back LDR, no external instruction access ............ 6-9 Figure 6-5 Simultaneous instruction and data requests ............6-10 Figure 6-6 Single STM, no instruction fetch ................6-11 Figure 6-7 Single LDM, no instruction access ................6-12 ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 10 Figure 6-12 SWP instruction ...................... 6-16 Figure 6-13 AHB 3:1 clocking example ..................6-17 Figure 6-14 ARM966E-S CLK to AHB HCLK sampling ............. 6-19 Figure 7-1 LDC/STC cycle timing ....................7-4 Figure 7-2 MCR/MRC transfer timing with busy-wait ..............7-8 Figure 7-3 Interlocked MCR/MRC timing with busy-wait ............
  • Page 11 Preface This preface introduces the ARM966E-S and its reference documentation. It contains the following sections: • About this document on page xii • Further reading on page xv • Feedback on page xvi. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 12: Preface

    Read this chapter for a description of the programmer’s model including a summary of the ARM966E-S coprocessor registers. Chapter 3 Memory Map Read this chapter for a description of the ARM966E-S fixed memory map implementation. Chapter 4 Tightly-coupled SRAM Read this chapter for a description of the requirements and operation of the tightly-coupled SRAM.
  • Page 13 Read this chapter for a description of the test methodology used for the ARM966E-S synthesized logic and tightly-coupled SRAM. Appendix A Signal Descriptions Read this appendix for a description of the ARM966E-S signals. Appendix B AC Parameters Read this appendix for a description of the timing parameters applicable to the ARM966E-S.

  • Page 14: Key To Timing Diagram Conventions

    Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 15: Further Reading

    Further reading This section lists publications by ARM Limited, and by third parties. If you would like further information on ARM products, or if you have questions not answered by this document, please contact or visit our web site at info@arm.com...

  • Page 16: Feedback

    Preface Feedback ARM Limited welcomes feedback both on the ARM966E-S, and on the documentation. Feedback on the ARM966E-S If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • a concise explanation of your comments...

  • Page 17: Chapter 1 Introduction

    Chapter 1 Introduction This chapter introduces the ARM966E-S processor. It contains the following sections: • About the ARM966E-S on page 1-2 • Microprocessor block diagram on page 1-3. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 18: About The Arm966E-S

    The ARM966E-S includes support for external coprocessors allowing floating point or other application-specific hardware acceleration to be added. To minimize die size and power consumption the ARM966E-S does not provide virtual to physical address mapping as this is not required by most embedded systems. A simple fixed memory map is implemented for the close-coupled local RAM, ideally suited to small, fast, real-time embedded control applications.

  • Page 19: Microprocessor Block Diagram

    Introduction Microprocessor block diagram The ARM966E-S block diagram is shown in Figure 1-1. DMA Controller interface AHB Peripherals Coprocessors Data Instruction Dout Dout System control External SRAM SRAM coprocessor Bus Interface Unit coprocessor (CP15) and write buffer interface Addr Addr...
  • Page 20 Introduction Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 21 Chapter 2 Programmer’s Model This chapter describes the programmer’s model for the ARM966E-S. It contains the following sections: • About the programmer’s model on page 2-2 • About the ARM9E-S programmer’s model on page 2-3 • ARM966E-S CP15 registers on page 2-4.

  • Page 22: Chapter 2 Programmer's Model

    Programmer’s Model About the programmer’s model The programmer’s model for the ARM966E-S macrocell primarily consists of the ARM9E-S core programmer’s model (see About the ARM9E-S programmer’s model on page 2-3). Additions to this model are required to control the operation of the ARM966E-S internal coprocessors, and any coprocessor connected to the external coprocessor interface.

  • Page 23: About The Arm9E-S Programmer's Model

    About the ARM9E-S programmer’s model The ARM9E-S processor core implements the ARM architecture v5T, that includes the 32-bit ARM instruction set and the 16-bit Thumb instruction set. For a description of both instruction sets, see the ARM Architecture Reference Manual. Contact ARM for complete descriptions of both instruction sets.

  • Page 24: Arm966E-S Cp15 Registers

    Register 7, Core control on page 2-7 • Register 15, Test on page 2-9. 2.3.1 CP15 register map summary The ARM966E-S incorporates CP15 for system control. The register map for CP15 is shown in Table 2-1. Table 2-1 CP15 register map Register Function...

  • Page 25: Table 2-2 Register 0, Id Code

    2.3.3 Register 1, Control register This register contains the global control bits of the ARM966E-S (see Table 2-3). All reserved bits must either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and write this register: MRC p15, 0, rd, c1, c0, 0;...
  • Page 26 Figure 3-1 on page 3-2, access the instruction SRAM. When LOW, all accesses to the instruction memory space access the AMBA AHB. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 27 Bit 12 is initialized either HIGH or LOW during system reset depending on the value of the input pin INITRAM. Bit 7, Endian Selects the endian configuration of the ARM966E-S. When this bit is HIGH, big-endian configuration is selected. When LOW, little-endian configuration is selected. This bit is cleared LOW during reset.
  • Page 28 Programmer’s Model Wait for interrupt This operation allows the ARM966E-S to enter a low-power standby mode. When the operation is invoked, the clock enable to the processor core is negated until either an interrupt or a debug request occurs. This function is invoked by a write to Register 7.

  • Page 29: Table 2-4 Register 13, Trace Process Identifier

    The contents of this register are replicated on the ETMPROCID pins of the ARM966E-S. The ETMPROCIDWR signal is set HIGH for a single clock cycle whenever this register is written to. Table 2-4 shows the trace process identifier for read and write.

  • Page 30: Table 2-6 Trace Control Register

    Instruction SRAM BIST running flag 15:5 Data SRAM BIST size Data SRAM BIST size Reserved (should be zero) Data SRAM BIST complete flag Reserved (should be zero) Data SRAM BIST fail flag 2-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 31: Table 2-8 Bist Size Encoding Examples

    000000 00111 512 bytes 000000 01000 1 KB 000000 01010 4 KB 000000 01111 128 KB 000000 11000 (maximum) 64 MB Note BIST size bits [31:26] should be zero. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 2-11...
  • Page 32 Reading the BIST control register returns the status of the BIST operations. See BIST of tightly-coupled SRAM on page 10-4 for a detailed description of the BIST support and the additional register 15 BIST registers. 2-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 33 Chapter 3 Memory Map This chapter describes the ARM966E-S fixed memory map implementation.It contains the following sections: • About the ARM966E-S memory map on page 3-2 • Tightly-coupled SRAM address space on page 3-3 • Bufferable write address space on page 3-4.

  • Page 34: About The Arm966E-S Memory Map

    Memory Map About the ARM966E-S memory map The ARM966E-S couples Instruction and Data SRAM memories of configurable size to the ARM9E-S core. This allows high-speed operation without incurring the performance and power penalties of accessing the system bus. A write buffer is used to minimize traffic on the AHB bus.

  • Page 35: Tightly-Coupled Sram Address Space

    INITRAM. Several boot options are available using INITRAM and the exception vectors location pin VINITHI. These are discussed in Using INITRAM input pin on page 4-4. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 36: Bufferable Write Address Space

    Memory Map Bufferable write address space The use of the ARM966E-S write buffer is controlled by both the CP15 control register and the fixed address map. When the ARM966E-S comes out of reset, the write buffer is disabled by default. All data writes to the AHB are performed as unbuffered.
  • Page 37 Chapter 4 Tightly-coupled SRAM This chapter describes the tightly-coupled SRAM in the ARM966E-S. It contains the following sections: • ARM966E-S SRAM requirements on page 4-2 • SRAM stall cycles on page 4-3 • Enabling the SRAM on page 4-4 •...

  • Page 38: Arm966E-S Sram Requirements

    Tightly-coupled SRAM ARM966E-S SRAM requirements The ARM966E-S tightly-coupled SRAM is built from blocks of ASIC library compiled SRAM. The Instruction SRAM (I-SRAM) and Data SRAM (D-SRAM) can each be any size from 0 bytes to 64MB, although to ease implementation the size must be an integer power of two.

  • Page 39: Sram Stall Cycles

    I-SRAM are pipelined by one clock cycle. Any stall requirement is detected by the SRAM control and factored into its response to the ARM966E-S system controller. The ARM9E-S SYSCLKEN input is then de-asserted until the SRAM has performed the access.

  • Page 40: Enabling The Sram

    If however, INITRAM is held HIGH during reset, both SRAM blocks are enabled when the ARM966E-S comes out of reset. This is normally used for a warm reset where the SRAM has already been programmed before the application of nRESET to the ARM966E-S.
  • Page 41 See ARM966E-S CP15 registers on page 2-4 for details of how to read and write the CP15 control register. When the I-SRAM has been enabled, all future ARM9E-S instruction fetches and data accesses to the I-SRAM address space as shown in Figure 3-1 on page 3-2 causes the I-SRAM to be accessed.
  • Page 42 Figure 3-1 on page 3-2, access the AHB. Read and write accesses to I-SRAM address space uses the I-SRAM or accesses the AHB depending on if it is enabled. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 43: Arm966E-S Sram Wrapper

    Tightly-coupled SRAM ARM966E-S SRAM wrapper The ARM966E-S allows you to have control over the size of the I-SRAM and D-SRAM (up to a maximum of 64MBytes each). It is not possible to have a single generic interface between the ARM966E-S and the SRAM, due to the large number of differing compiled SRAM that can be integrated into an ARM966E-S system, potentially each with a unique interface.

  • Page 44: Figure 4-3 Onesegx32 Interface

    ByteWrite signals. Your own library RAMs are instantiated inside InstrRAM.v DataRAM.v 4.4.1 Example SRAM interfaces The example wrapper supplied by ARM contains three RAM interface examples. All of the interface modifications are done in the and the blocks for the IRamIF.v DRamIF.v...

  • Page 45: Figure 4-4 Foursegx32 Interface

    The use of asynchronous RAMs is not recommended due to the increased power consumption of this solution. Note The wrapper RTL does not support asynchronous RAMs. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 46 In Figure 4-5 on page 4-11 ByteWrite[3:0] is used (inside IRamIF.v) to decode each word-wide chip select into four separate chip select signals, one for each byte of the word. 4-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 47: Figure 4-5 Foursegx8 Interface

    2Kx8 [11] [15] 2Kx8 2Kx8 2Kx8 2Kx8 [10] [14] 2Kx8 2Kx8 2Kx8 2Kx8 [13] WriteEnable 2Kx8 2Kx8 2Kx8 2Kx8 ChipSelect[15:0] [12] IRamIF.v OutputSelect[1:0] IRData[31:0] Figure 4-5 FOURSEGX8 interface ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 4-11...
  • Page 48 Tightly-coupled SRAM 4-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 49 Chapter 5 Direct Memory Access (DMA) This chapter describes the optional DMA interface in the ARM966E-S. It contains the following sections: • About the DMA interface on page 5-2 • Timing interface on page 5-5 • DMAENABLE setup and hold cycles on page 5-11 •...

  • Page 50: Chapter 5 Direct Memory Access (Dma)

    Direct Memory Access (DMA) About the DMA interface A DMA port is provided on the ARM966E-S. You can connect this port to the D-SRAM in the ARM966E-S. This allows direct access to the D-SRAM from outside the ARM966E-S boundary. If this feature is not required the DMA port is tied off in the RTL and made redundant.

  • Page 51: Table 5-1 Simultaneous Access Behavior

    The behavior of accessing the same memory locations simultaneously is either undefined or illegal. Simultaneous access behavior is summarized in Table 5-1. Table 5-1 Simultaneous access behavior Core behavior access access Read Read Valid ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 52: Figure 5-2 Dual-Port Ram Dma Interface

    Write Write Illegal Figure 5-2 shows how the ARM966E-S DMA port interfaces to a dual-port RAM. For modelling purposes, the dual-port DMA solution also supports the single-port access route. Single-port access reduces performance in the dual-port solution and is unlikely to be used, so to prevent the core from being stalled, DMAWait must be tied LOW.

  • Page 53: Timing Interface

    Timing interface To ease the system integration task and to provide RAM independent timings, the ARM966E-S registers all DMA inputs and outputs. This section details the behavior of the ARM966E-S for DMA read and writes to single and dual-port RAMs.
  • Page 54 DMAReady is asserted. Read data is driven on DMARData in the third cycle after the read address is sampled by the ARM966E-S (one cycle to register the address, one cycle for the RAM read and one cycle for registering the RAM read data). The first read address, DMAAddr, is registered by the ARM966E-S on the next rising clock edge after DMAReady is asserted.

  • Page 55: Figure 5-4 Single-Port Ram Dma Writes

    DMAAddr, must be valid in the same cycle. The read data, DMARData, is returned in the third cycle after the request is registered by the ARM966E-S (one cycle to register the request, one cycle to read the RAM, and one cycle to register the output data).

  • Page 56: Figure 5-5 Dual-Port Dma Reads

    Note Because the ARM966E-S core does not need to be stalled for dual-port DMA accesses, the DMA controller can access the data RAM continuously. DMAWait must be tied LOW otherwise the DMA access is by the first port of the RAM and the interface behaves as described in Single-port RAM writes on page 5-6.

  • Page 57: Figure 5-6 Dual-Port Ram Dma Writes

    RAM was single or dual-port, the behavior of DMAENABLE, DMAWait, and DMAReady is described in sections Single-port RAM reads on page 5-5 to Dual-port RAM writes on page 5-8. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 58: Figure 5-7 Mixed Dma Read And Write

    Direct Memory Access (DMA) DMAnREQ DMAnRW DMAAddr WD_A2 WD_A4 DMAWData RD_A1 RD_A3 DMARData Figure 5-7 Mixed DMA read and write 5-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 59: Dmaenable Setup And Hold Cycles

    Single-port RAM DMA read Single-port RAM DMA write To reduce power consumption, DMAENABLE must be taken LOW when DMA accesses are not taking place or if DMA is not implemented. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 5-11...

  • Page 60: Summary Of Signal Behavior

    Must be registered by Do not care. DMA controller the DMA controller so (Output) because it always has that it knows when the access to the RAM. ARM966E-S has been stalled. 5-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 61: About The Biu And Write Buffer

    Chapter 6 Bus Interface Unit This chapter describes the ARM966E-S Bus Interface Unit (BIU) and write buffer. It contains the following sections: • About the BIU and write buffer on page 6-2 • Write buffer operation on page 6-3 •...

  • Page 62: About The Biu And Write Buffer

    See the AMBA Rev 2.0 AHB specification for full details of this bus architecture. The ARM966E-S BIU implements a fully-compliant AHB bus master interface and incorporates a write buffer to increase system performance. The BIU is the link between the ARM9E-S core with its tightly-coupled SRAM and the external AHB memory.

  • Page 63: Write Buffer Operation

    Bus Interface Unit Write buffer operation The ARM966E-S implements a 12-entry write buffer, where the entries can be address or data depending on the nature of the writes being executed by the ARM9E-S core. The write buffer helps to decouple the core from the wait cycles incurred when accessing the AHB.

  • Page 64: Figure 6-1 Write Buffer Fifo Content Example

    The write buffer can drain naturally where AHB writes occur whenever data is committed to the FIFO. The core is only stalled, if the write buffer overflows. However, there are times when a complete drain of the write buffer is enforced. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 65 Additionally, the AHB can be run at a lower rate than the ARM966E-S system introducing extra delay to the buffered write process. This can lead to the core trying to commit data at a higher rate than the FIFO can be drained, resulting in the FIFO becoming full.
  • Page 66 If the programmer requires no more buffered writes to occur following write buffer disable or a instruction, the write buffer must first be drained with wait for interrupt command. drain write buffer Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 67: Ahb Bus Master Interface

    6.3.2 ARM966E-S transfer descriptions The ARM966E-S BIU performs a subset of the possible AHB bus transfers available. This section describes the transfers that can be performed and some back-to-back transfer cases: •...

  • Page 68: Figure 6-2 Sequential Instruction Fetches, After Being Granted The Bus

    Bus request At the start of every AHB access, the ARM966E-S requests access to the bus by asserting HBUSREQ to the arbiter. It must then wait for an acknowledge signal from the arbiter (HGRANT), before beginning the transfer on the next rising edge of HCLK.

  • Page 69: Figure 6-3 Sequential Instruction Fetches, No Ahb Data Access Required

    ID-2 ID-3 ID-4 HRDATA HREADY Figure 6-3 Sequential instruction fetches, no AHB data access required Back-to-back LDR or STR accesses Figure 6-4 shows ARM966E-S bus activity when a sequence of LDR instructions is executed. NONSEQ IDLE NONSEQ IDLE NONSEQ IDLE...

  • Page 70: Figure 6-5 Simultaneous Instruction And Data Requests

    Figure 6-5 Simultaneous instruction and data requests During the cycle that [IA-3] is first driven onto HADDR, the BIU detects a simultaneous data request. [IA-3] fetch is suspended until the data access has completed. 6-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 71: Figure 6-6 Single Stm, No Instruction Fetch

    AHB data access, also results in one IDLE cycle being inserted between the two accesses. LDM timing Figure 6-7 on page 6-12 shows the timing for an instruction, transferring three words. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 6-11...

  • Page 72: Figure 6-7 Single Ldm, No Instruction Access

    The instruction read begins with a NONSEQ/IDLE sequence after the final sequential data access. In this example, subsequent instruction fetches are sequential. 6-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 73: Figure 6-8 Single Stm, Followed By Sequential Instruction Fetch

    A single IDLE cycle is inserted after the final sequential data access, and instruction fetch begins with a NONSEQ/IDLE sequence. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 6-13...

  • Page 74: Figure 6-9 Single Ldm Followed By Sequential Instruction Fetch

    STM crossing a 1KB boundary AMBA Rev.2 Specification states that sequential accesses must not cross 1KB boundaries. The ARM966E-S splits sequential accesses that cross a 1KB boundary into two sets of separate accesses. Figure 6-10 on page 6-15 shows bus activity when a writing four words, crosses a 1KB boundary.

  • Page 75: Figure 6-10 Single Stm, Crossing A 1Kb Boundary

    IDLE cycles. NONSEQ IDLE NONSEQ IDLE HTRANS DA-1 DA-2 DA-3 DA-4 HADDR HWRITE DD-1 DD-2 DD-3 DD-4 HRDATA HREADY Figure 6-11 Single LDM, crossing a 1KB boundary ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 6-15...

  • Page 76: Figure 6-12 Swp Instruction

    Figure 6-12 shows a instruction. IDLE NONSEQ IDLE NONSEQ IDLE HTRANS A_SWP HADDR A_SWP HRDATA HWRITE SWP_D2 HWDATA HLOCK Figure 6-12 SWP instruction 6-16 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 77: Ahb Clocking

    The ARM966E-S design uses a single rising edge clock CLK to time all internal activity. In many systems where the ARM966E-S is embedded, it is desirable to run the AHB at a lower rate. To support this requirement, the ARM966E-S requires a clock enable, HCLKEN, to time AHB transfers.
  • Page 78 If the slave being accessed at the HCLK rate has a multi-cycle response, the HREADY input to the ARM966E-S is driven LOW until the data is ready to be returned. The BIU must therefore perform a logical AND on the HREADY response with HCLKEN to detect that the AHB transfer has completed.

  • Page 79: Figure 6-14 Arm966E-S Clk To Ahb Hclk Sampling

    In this example, the slave peripheral has an input setup and hold, and an output hold and valid time relative to HCLK. The ARM966E-S has an input setup and hold, and an output hold and valid relative to CLK’, the clock at the bottom of the clock tree. Clock tree insertion must be used to position the HCLK to match CLK’...
  • Page 80 Bus Interface Unit 6-20 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 81 Chapter 7 Coprocessor Interface This chapter describes the ARM966E-S pipelined coprocessor interface. It contains the following sections: • About the coprocessor interface on page 7-2 • LDC/STC on page 7-4 • MCR/MRC on page 7-8 • Interlocked MCR on page 7-9 •...

  • Page 82: Chapter 7 Coprocessor Interface

    The interface differs from the basic ARM9E-S coprocessor interface. To ease integration of an external coprocessor, the interface from the ARM966E-S to the coprocessor has been pipelined by a single clock cycle.
  • Page 83 The coprocessor data processing instruction ( ) is used for coprocessor instructions that do not operate on values in ARM registers or in main memory. One example is a floating-point multiply instruction for a floating-point accelerator processor. To enable coprocessors to continue execution of...

  • Page 84: Ldc/Stc

    LDC/STC instructions are used respectively to transfer data to and from external coprocessor registers and memory. In the case of the ARM966E-S, the memory can be either tightly-coupled SRAM or AHB depending on the address range of the access and SRAM enable.
  • Page 85 ARM9E-S processor core must stall until the coprocessor can catch up. This is known as the busy-wait condition. In this case, the ARM9E-S processor core loops in an IDLE state waiting for ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 86: Table 7-1 Handshake Encoding

    ARM9E-S processor core outputs the address for the LDC/STC. Also in this cycle, DnMREQ is driven LOW, indicating to the ARM966E-S memory system that a memory access is required at the data end of the device. The timing for the data on CPDOUT and CPDIN is shown in Figure 7-1 on page 7-4.
  • Page 87 Meaning WAIT LAST Note If an external coprocessor is not attached in the ARM966E-S embedded system, the CHSDE[1:0] and CHSEX[1:0] handshake inputs must be tied off to indicate ABSENT. 7.2.3 Multiple external coprocessors If multiple external coprocessors are to be attached to the ARM966E-S interface, the handshaking signals can be combined by ANDing bit1, and ORing bit0.

  • Page 88: Mcr/Mrc

    CPDOUT[31:0] bus is driven with the registered data. In the case of a CPDIN[31:0] is sampled at the end of the ARM9E-S core Memory stage and written to the destination register during the next cycle. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 89: Interlocked Mcr

    (WAIT) (LAST) pipeline MCR/MRC CPINSTR[31:0] nCPMREQ CPPASS CPLATECANCEL WAIT WAIT CHSDE[1:0] LAST Ignored CHSEX[1:0] Coproc to ARM CPDIN[31:0] ARM to coproc CPDOUT[31:0] Figure 7-3 Interlocked MCR/MRC timing with busy-wait ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 90: Cdp

    CPASS. In the following cycle CPLATECANCEL is asserted. This causes the coprocessor to terminate execution of the instruction and for it to cause no state changes to the coprocessor. 7-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 91: Privileged Instructions

    The first two CHSDE[1:0] responses are ignored by the ARM9E-S because it is only the final CHSDE[1:0] response, as the instruction moves from Decode into Execute, that counts. This allows the coprocessor to change its response when nCPTRANS changes. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 7-11...

  • Page 92: Busy-Waiting And Interrupts

    Abandoned Execute Execute Execute Execute Coprocessor (WAIT) (WAIT) (WAIT) (WAIT) pipeline INSTR CPINSTR[31:0] nCPMREQ CPPASS CPLATECANCEL WAIT CHSDE[1:0] WAIT WAIT WAIT Ignored CHSEX[1:0] Figure 7-6 Busy-waiting and interrupts 7-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 93 Chapter 8 Debug Support This chapter describes the ARM966E-S debug interface. It contains the following sections: • About the debug interface on page 8-2 • Debug systems on page 8-4 • ARM966E-S scan chain 15 on page 8-7 • Debug interface signals on page 8-9 •...

  • Page 94: About The Debug Interface

    This is known as halt mode operation and allows the internal state of the ARM9E-S core, ARM966E-S system, and external state of the AHB to be examined while all other system activity continues as normal. When debug is complete, the ARM9E-S restores the core and system state, and resumes program execution.

  • Page 95: Figure 8-1 Clock Synchronization

    Debug Support 8.1.2 Clocks The system and test clocks must be synchronized externally to the ARM966E-S macrocell. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. To synchronize off-chip debug clocking with the ARM966E-S macrocell requires a three-stage synchronizer.

  • Page 96: Debug Systems

    8.2.2 The protocol converter An interface, such as a parallel port, connects the debug host to the ARM966E-S development system. The messages broadcast over this connection must be converted to the interface signals of the ARM966E-S. The protocol converter performs the conversion.

  • Page 97: Figure 8-3 Arm9E-S Block Diagram

    15. This is used for debug access to the CP15 register bank, to allow the system state within the ARM966E-S to be configured while in debug state, for instance to enable or disable the SRAM before performing a debug load or store.
  • Page 98 Debug Support The rest of this chapter describes the ARM9E-S and ARM966E-S hardware debug extensions. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 99: Arm966E-S Scan Chain 15

    Scan chain 15 is provided to allow debug access to the CP15 register bank, to allow the system state within the ARM966E-S to be configured while in debug state. The order of scan chain 15 from the DBGTDI input to the DBGTDO output is shown...
  • Page 100 Table 8-2 on page 8-7. These bits are not used in the BIST Address registers and so there are no debug restrictions when accessing these registers. The ability to control the ARM966E-S system state through scan chain 15 provides extra debug visibility. For example, if the debugger wishes to compare the contents of...

  • Page 101: Debug Interface Signals

    DBGIEBKPT, DBGDEWPT, and EDBGRQ are system requests for the ARM966E-S to enter debug state • DBGACK is used by the ARM966E-S to flag back to the system that it is in debug state. 8.4.1 Entry into debug state on breakpoint Any instruction being fetched from memory is sampled at the end of a cycle.

  • Page 102: Figure 8-4 Breakpoint Timing

    For this reason, as soon as the processor enters stop-mode debug state, interrupts are disabled, although the state of the I and F bits in the Program Status Register (PSR) are not affected. 8-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 103: Figure 8-5 Watchpoint Entry With Data Processing Instruction

    When the debugging session is complete, normal continuation involves a return to instruction 5, the next instruction in the code sequence to be executed. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 8-11...

  • Page 104: Figure 8-6 Watchpoint Entry With Branch

    If there is an interrupt pending, again the ARM9E-S allows the exception entry sequence to occur and then enters debug state. 8-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 105 When the ARM9E-S is in debug state, both memory interfaces indicate internal cycles. This ensures that both the tightly-coupled SRAM within the ARM966E-S and the AHB interface are quiescent, allowing the rest of the AHB system to ignore the ARM9E-S and function as normal.

  • Page 106: Arm9E-S Core Clock Domains

    • DBGTCKEN controls debug operations. During normal operation, SYSCLKEN conditions CLK to clock the core. When the ARM966E-S is in debug state, DBGTCKEN conditions CLK to clock the core. 8-14 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 107: Determining The Core And System State

    Debug Support Determining the core and system state When the ARM966E-S is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline. Before you can examine the core and system state, the debugger must determine whether the processor entered debug from Thumb state or ARM state, by examining bit 4 of the EmbeddedICE-RT debug status register.

  • Page 108: About The Embeddedice-Rt

    • debug communications channel. The debug control register and the debug status register provide overall control of EmbeddedICE-RT operation. 8-16 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 109 Any bit can be masked so that its value does not affect the comparison. Each watchpoint unit can be configured to be either a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be data-dependent. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 8-17...

  • Page 110: Disabling Embeddedice-Rt

    Caution Hard-wiring the DBGEN input LOW permanently disables debug access. When DBGEN is LOW, it inhibits DBGDEWPT, DBGIEBKPT, and EDBGRQ to the core, and DBGACK from the ARM966E-S is always LOW. 8-18 Copyright © 2000 ARM Limited. All rights reserved.

  • Page 111: The Debug Communications Channel

    The debug communications channel status register is read-only. It controls synchronized handshaking between the processor and the debugger. The debug communications channel status register is shown in Figure 8-8 on page 8-20. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 8-19...

  • Page 112: Figure 8-8 Debug Communications Channel Status Register

    This writes the value in Rn to the communications data write MCR p14, 0, Rn, c1, c0 register. MRC p14, 0, Rd, c1, c0 This returns the debug data read register into Rd. 8-20 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 113: Figure 8-9 Coprocessor 14 Debug Status Register Format

    When the processor wishes to send a message to the debugger, it must check the communications data write register is free for use by finding out whether the W bit of the debug communications control register is clear. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 8-21...
  • Page 114 R bit in the debug communications control register. When the debugger polls this register and sees that the R bit is clear, the data is taken, and the process can be repeated. 8-22 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 115: Monitor Mode Debug

    EmbeddedICE-RT logic is configured so that a breakpoint or watchpoint causes the ARM to enter abort mode, taking the Prefetch Abort or Data Abort vectors respectively. When the ARM is configured for real-time debugging you must be aware of the following restrictions: •...
  • Page 116 Disable that watchpoint unit using the control register for that watchpoint unit Change the other registers Re-enable the watchpoint unit by rewriting the control register. 8-24 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 117: Debug Additional Reading

    Debug additional reading A more detailed description of the ARM9E-S debug features and JTAG interface is provided in the ARM9E-S Technical Reference Manual, Appendix D Debug in Depth. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 8-25...
  • Page 118 Debug Support 8-26 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 119: Chapter 9 Embedded Trace Macrocell Interface

    Chapter 9 Embedded Trace Macrocell Interface This chapter describes the ARM966E-S Embedded Trace Macrocell (ETM) interface. It contains the following sections: • About the ETM interface on page 9-2 • Enabling the ETM interface on page 9-3. ARM DDI 0186A...

  • Page 120: About The Etm Interface

    The ARM966E-S supports the connection of an external Embedded Trace Module (ETM) to provide real time code tracing of the ARM966E-S in an embedded system. The ETM interface is primarily one way. In order to provide code tracing, the ETM block must be able to monitor various ARM9E-S inputs and outputs.

  • Page 121: Enabling The Etm Interface

    The ETMEN input is usually driven by the ETM, and driven HIGH once the ETM is programmed using its TAP controller. Note If an ETM is not used in an embedded ARM966E-S design, the ETMEN input must be tied LOW to save power. ARM DDI 0186A...

  • Page 122: Arm966E-S Trace Support Features

    9.3.1 FIFOFULL The signal, FIFOFULL, is an input to the ARM966E-S driven by the ETM9. Whenever the programmed upper watermark of the ETM FIFO is filled, FIFOFULL is asserted. The ARM966E-S uses FIFOFULL to stall the ARM9E-S core, preventing trace loss.
  • Page 123 Chapter 10 Test Support This chapter describes the test methodology employed for the ARM966E-S synthesized logic and tightly-coupled SRAM. It contains the following sections: • About the ARM966E-S test methodology on page 10-2 • Scan insertion and ATPG on page 10-3 •...

  • Page 124: Chapter 10 Test Support

    To achieve a high level of fault coverage, scan insertion and ATPG techniques are used on the ARM9E-S core and ARM966E-S control logic as part of the synthesis flow. BIST is used to provide high fault coverage of the compiled SRAM.

  • Page 125: Scan Insertion And Atpg

    10.2.1 ARM966E-S INTEST wrapper To facilitate testing of the shadow logic between the ARM966E-S scan chains and the scan chains in an OEM ASIC, a synthesis option allows an INTEST wrapper to be inserted into the ARM966E-S. The INTEST wrapper is a scan chain around the boundary of the ARM966E-S, connecting to all input and output pins.

  • Page 126: Bist Of Tightly-Coupled Sram

    CP15 register 15 address space. For details of the instructions used to access these registers, see Register 15, Test on page 2-9. Access to these registers is also available in debug mode, see ARM966E-S scan chain 15 on page 8-7.

  • Page 127: Table 10-1 Instruction Bist Address And General Registers

    IBIST start address IBIST address register IBIST fail address IBIST peek/poke address IBIST general register IBIST fail data IBIST seed data IBIST general register IBIST peek data IBIST poke data ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 10-5...

  • Page 128: Table 10-2 Data Bist Address And General Registers

    The BIST test pauses at predetermined points of the BIST algorithm, for instance when the algorithm has reached the top or the bottom of the memory array being tested. 10-6 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 129 User pause mode is provided for production test debugging to shorten a test by pausing the algorithm early. The auto pause mechanism is recommended to provide or BIST hardware testing for all other occasions. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 10-7...
  • Page 130 Test Support 10-8 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 131 Chapter 11 Instruction cycle timings This chapter describes the instruction cycle timings for the ARM966E-S. It contains the following sections: • Introduction to instruction cycle timings on page 11-2 • When stall cycles do not occur on page 11-3 •...

  • Page 132: Chapter 11 Instruction Cycle Timings

    In a system such as the ARM966E-S, the CLKEN input to the ARM9E-S core might be pulled LOW to stall the processor until the memory system is able to respond to the access.

  • Page 133: When Stall Cycles Do Not Occur

    ARM9E-S core can run within the ARM966E-S with no stall cycles introduced by the system controller. When this is the case, the ARM966E-S is running at peak efficiency and the instruction cycles exactly match those quoted in the ARM9E-S Technical Reference Manual.

  • Page 134: Tightly-Coupled Sram Cycles

    Stall due to second cycle of store instruction fetch , instruction fetch in Simultaneous instruction fetch request must wait for parallel with final store second cycle of final write to complete 11-4 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 135: Table 11-2 D-Sram Access

    STR/STM LDR/LDM performed Note All internal SRAM stall cycles are in terms of the CLK and are therefore not affected by the speed of the external AHB interface. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 11-5...

  • Page 136: Ahb Memory Access Cycles

    11.4.1 Synchronization penalty At the start of an AHB access, the BIU within the ARM966E-S must wait for the first rising edge of HCLK (the HCLKEN input is true) before it can broadcast the necessary AHB control and address information for the access. This delay is the synchronization penalty.

  • Page 137: Table 11-4 Ahb Read And Unbuffered Write Transfer Cycles

    HCLK cycle required for an IDLE cycle (=R) Number of words accessed by the transfer Table 11-4 lists the types of AHB transfers performed by the ARM966E-S and the number of CLK cycles required to perform them. This table indicates cycles where the ARM9E-S core must be stalled until one or more AHB accesses have completed, that is, for reads and unbuffered writes.
  • Page 138 However, whenever a load or instruction fetch to the AHB is required, the core is stalled and the write buffer drained before program execution can continue. 11-8 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 139: Table 11-5 Ahb Buffered Writes Cycles

    Last in write buffer drain followed 2N+I Optimization replaces IDLE cycle by instruction fetch after store with NONSEQ of instruction fetch ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. 11-9...

  • Page 140: Interrupt Latency Calculation

    Technical Reference Manual. The number quoted assumes that the CLKEN input to the core is HIGH, ensuring no stall cycles. In the ARM966E-S, the best-case figure could match the latency quoted for the ARM9E-S core, if the necessary data and instructions were already in the D-SRAM and I-SRAM respectively.

  • Page 141: Table 11-7 Interrupt Latency Calculated Examples

    AHB slave responses that might exist in the AHB system to which the ARM966E-S interfaces. Table 11-7 gives examples of interrupt latency for systems with different CLK to HCLK ratios. For each system, slaves can have different response times to NONSEQ and SEQ transfers.
  • Page 142 Instruction cycle timings 11-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 143: Table A-5 Miscellaneous Signals

    Appendix A Signal Descriptions This appendix describes the ARM966E-S signals. It contains the following sections: • Signal properties and requirements on page A-2 • Clock interface signals on page A-3 • AHB signals on page A-4 • Coprocessor interface signals on page A-6 •...

  • Page 144: Signal Properties And Requirements

    Signal Descriptions Signal properties and requirements In order to ensure ease of integration of the ARM966E-S into embedded applications and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity •...

  • Page 145: Clock Interface Signals

    Signal Descriptions Clock interface signals Table A-1 describes the ARM966E-S clock interface signals. Table A-1 Clock interface signals Name Direction Description Input This clock times all operations in the ARM966E-S design. All outputs change from the rising edge and System clock all inputs are sampled on the rising edge.

  • Page 146: Ahb Signals

    (01--). Bit [3] is driven to 0 indicating not cacheable. HWDATA[31:0] Output The 32-bit write data bus is used to transfer data from the ARM966E-S to a selected bus slave during write Write data bus operations. HRDATA[31:0] Input...
  • Page 147 Ownership of the address and Bus grant control signals changes at the end of a transfer when HREADY is HIGH, so the ARM966E-S gets access to the bus when both HREADY and HGRANT are HIGH. ARM DDI 0186A...

  • Page 148: Coprocessor Interface Signals

    Signal Descriptions Coprocessor interface signals Table A-3 describes the ARM966E-S coprocessor interface signals. Table A-3 Coprocessor interface signals Name Direction Description CPCLKEN Output Synchronous enable for coprocessor pipeline follower. When HIGH on the rising edge of CLK the Coprocessor clock pipeline follower logic is able to advance.
  • Page 149 Not coprocessor must enter the coprocessor pipeline. instruction request nCPTRANS Output When LOW indicates that the ARM966E-S is in User mode. When HIGH indicates that the ARM966E-S is Not coprocessor in privileged mode. Sampled by the coprocessor memory translate pipeline follower.

  • Page 150: Debug Signals

    Signal Descriptions Debug signals Table A-4 describes the ARM966E-S debug signals. Table A-4 Debug signals Name Direction Description DBGIR[3:0] Output These four bits reflect the current instruction loaded into the TAP controller control register. These bits TAP controller change when the TAP controller is in the instruction register UPDATE-IR state.
  • Page 151 EmbeddedICE currently present on the address, data and control Rangeout buses. This signal is independent of the state of the watchpoint enable control bit. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 152 Asserted by external hardware to halt execution of the processor for debug purposes. If HIGH at the end Instruction of an instruction fetch, it causes the ARM966E-S to breakpoint enter debug state if that instruction reaches the Execute stage of the processor pipeline.

  • Page 153: Miscellaneous Signals

    Signal Descriptions Miscellaneous signals Table A-5 describes the ARM966E-S miscellaneous signals. Table A-5 Miscellaneous signals Name Direction Description nFIQ Input This is the Fast Interrupt Request signal. This signal must be synchronous to CLK. Not fast interrupt request nIRQ Input This is the Interrupt Request signal.

  • Page 154: Etm Interface Signals

    Signal Descriptions ETM interface signals Table A-6 describes the ARM966E-S ETM interface signals. Table A-6 ETM interface signals Name Direction Description ETMEN Input Synchronous ETM interface enable. This signal must be tied LOW if an ETM is not used. FIFOFULL Input Asserted when ETM FIFO fills.
  • Page 155 Coprocessor instruction execute indication for the ETM. ETMLATECANCEL Output Coprocessor late cancel indication for the ETM. ETMPROCID Output Process ID for the ETM. ETMPROCIDWR Output Asserted when ETMPROCID is written. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. A-13...

  • Page 156: Intest Wrapper Signals

    Selects the INTEST wrapper scan chain as the source for ARM966E-S inputs. SERIALEN Input Enables the INTEST wrapper BIST activation mode where the scan chain is used to apply serialized ARM instructions to the ARM966E-S to activate BIST test of the tightly-coupled SRAM. ICAPTUREEN Input 1 = INTEST wrapper in INTEST mode 0 = INTEST wrapper in EXTEST mode.

  • Page 157: Dma Signals

    DMA write data. DMAWait Input DMA Wait. Used to stall the ARM966E-S to allow a DMA access to take place. This functionality is only required if the data RAM is single-port. This signal must be tied LOW if the data RAM is dual-port.
  • Page 158 Signal Descriptions A-16 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 159: Appendix Bac Parameters

    Appendix B AC Parameters This appendix describes the AC timing parameters for the ARM966E-S. It contains the following sections: • Timing diagrams on page B-2 • AC timing parameter definitions on page B-12. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 160: B.1 Timing Diagrams

    Clock, reset and AHB enable timing parameters are shown in Figure B-1. Figure B-1 Clock, reset and AHB enable timing AHB bus request and grant related timing parameters are shown in Figure B-2 on page B-3. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 161: Figure B-2 Ahb Bus Request And Grant Related Timing

    AC Parameters Figure B-2 AHB bus request and grant related timing AHB bus master timing parameters are shown in Figure B-3 on page B-4. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 162: Figure B-3 Ahb Bus Master Timing

    AC Parameters Figure B-3 AHB bus master timing Coprocessor interface timing parameters are shown in Figure B-4 on page B-5. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 163: Figure B-4 Coprocessor Interface Timing

    AC Parameters Figure B-4 Coprocessor interface timing Debug interface timing parameters are shown in Figure B-5 on page B-6. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 164: Figure B-5 Debug Interface Timing

    AC Parameters Figure B-5 Debug interface timing JTAG interface timing parameters are shown in Figure B-6 on page B-7. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 165: Figure B-6 Jtag Interface Timing

    AC Parameters Figure B-6 JTAG interface timing A combinatorial path timing parameter exists from the DBGSDOUT input to the DBGTDO output. This is shown in Figure B-7 on page B-8. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 166: Figure B-7 Dbgsdout To Dbgtdo Timing

    Exception and configuration timing parameters are shown in Figure B-8. Figure B-8 Exception and configuration timing The INTEST wrapper timing parameters are shown in Figure B-9 on page B-9. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 167: Figure B-9 Intest Wrapper Timing

    TESTEN istesten ihtesten SERIALEN isserialen ihserialen ICAPTUREEN ihcaptureen iscapturee Figure B-9 INTEST wrapper timing The ETM interface timing parameters are shown in Figure B-10 on page B-10. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 168: Figure B-10 Etm Interface Timing

    ETMCHSD[1:0] ETMPASS ATMPLATECANCEL ovetmcfg ohetmcfg ETMDBGACK ATMRNGOUT[1:0] ETMBIGEND ovetmcpif ohetmcpif ETMHIVECS ETMPROCID ATMPRODCDWR ovetmdbg ohetmdbg ETMEN isetmen ihetmen FIFOFULL isetmfifofull ihetmfifull Figure B-10 ETM interface timing B-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 169: Figure B-11 Dma Interface Timing

    AC Parameters The DMA interface timing parameters are shown in Figure B-11 DMAReady DMARData ovdma ohdma DMAENABLE DMAnREQ DMAA DMAMAS DMAD isdma ihdma DMAWait Figure B-11 DMA interface timing ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. B-11...

  • Page 170: Ac Timing Parameter Definitions

    Rising CLK to HADDR[31:0] valid HADDR[31:0] hold time from rising CLK >0% Rising CLK to AHB control signals valid ovct AHB control signals hold time from rising CLK >0% ohctl B-12 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 171 Rising CLK to CPDOUT[31:0] valid ovcprd CPDOUT[31:0] hold time from rising CLK >0% ohcprd CPDIN[31:0] input setup time to rising CLK iscpwr CPDIN[31:0] input hold time from rising CLK ihcpwr ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. B-13...
  • Page 172 Rising CLK to DBGSDIN valid ovsdin DBGSDIN hold time from rising CLK >0% ohsdin Rising CLK to DBGTDO valid ovtdo DBGTDO hold time from rising CLK >0% ohtdo B-14 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 173 SI input setup time to rising CLK issi SI input hold time from rising CLK ihsi SCANEN input setup time to rising CLK isscanen SCANEN input hold time from rising CLK ihscanen ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. B-15...
  • Page 174 ETM coprocessor signals hold time from rising CLK >0% ohetmcpif Rising CLK to ETM debug signals valid ovetmdbg ETM debug signals hold time from rising CLK >0% ohetmdbg B-16 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 175 The INTEST wrapper inputs and outputs are specified as 95% of the cycle as they are production test related and expected to operate at typically 50% of the functional clock rate. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. B-17...
  • Page 176 AC Parameters B-18 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 177: Appendix Csram Stall Cycles

    Appendix C SRAM Stall Cycles This appendix describes the tightly-coupled SRAM in the ARM966E-S. It contains the following section: • About SRAM stall cycles on page C-2. For details of the ARM9E-S interface signals referenced in this section, refer to the ARM9E-S Technical Reference Manual.

  • Page 178: About Sram Stall Cycles

    SRAMs and additional stall mechanism attributed to the I-SRAM only. Any stall requirement is detected by the SRAM control and factored into its response to the ARM966E-S system controller. The ARM9E-S SYSCLKEN input is then deasserted until the SRAM has performed the access.

  • Page 179: Simultaneous Instruction Fetch, Data Read

    Simultaneous instruction fetch, data read The ARM9E-S data interface is able to access the I-SRAM for programming purposes and for access to literal tables during program execution. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 180 To maximize the I-SRAM interface frequency performance, data read requests to this RAM are pipelined. This adds a stall cycle for every data read instruction. An example of a data read from the I-SRAM is shown in on page C-5. Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 181: Data Read From I-Sram

    Data reads to the I-SRAM are pipelined. An instruction fetch in the cycle after a data read request coincides with the stalled data read and so the instruction fetch is stalled for 1 cycle. This is shown in on page C-6. ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 182: Simultaneous Instruction Fetch, Data Write

    I-SRAM address space, two stall cycles occur. The first cycle allows for the pipelined write, the second cycle allows for the instruction fetch. The core cannot be enabled until both accesses have completed (see Figure C-6 on page C-7). Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 183: I-Sram Data Write Followed By Instruction Fetch

    The instruction fetch must be held off until the write has completed, requiring that the ARM9E-S core is stalled for a cycle (see Figure C-7 on page C-8). ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.

  • Page 184: I-Sram Write Followed By Instruction Fetch, Data Write

    However, the core must be stalled until both the second write and instruction fetch have completed, so there are two stall cycles (see Figure C-8 on page C-9). Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

  • Page 185: I-Sram Write Followed By Instruction Fetch, Data Read

    I-SRAM control behaves differently. The first write must complete before the data read can be performed. The instruction fetch can then be performed in the next cycle (see Figure C-9 on page C-10). ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved.
  • Page 186 Addr B (I fetch) IA[31:1] Addr A Addr B I-SRAM Addr Read data (A) RDATA[31:0] Read Instr (B) INSTR[31:0] SYSCLKEN Figure C-9 I-SRAM write followed by instruction fetch, data read C-10 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 187 Data SRAM 3-3 Prefetch Abort 8-10 Coprocessor enable 2-7 timing 8-10 handshake signals 7-5 DBGACK 8-9, 8-18, A-9 Bufferable write address space 3-4 handshake states 7-5 DBGDEWPT 8-18, A-10 ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. Index-1...
  • Page 188 ARM9E-S 8-13 ETMINSTREXEC A-12 breakpoints 8-9 ETMISEQ A-12 watchpoints 8-11 ETMITBIT A-12 Disabling EmbeddedICE-RT 8-18 ETMLATECANCEL A-13 ETMnWAIT A-12 Low-power mode 2-8 interface 5-1 ETMPASS A-13 Index-2 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...
  • Page 189 DMAD A-15 ICAPTUREEN A-14 DMAENABLE A-15 INITRAM A-11 SCANEN A-14 DMAMAS A-15 nCPMREQ A-7 Serial interface, JTAG 8-2, 8-5 DMAnREQ A-15 nCPTRANS A-7 SERIALEN A-14 DMAnRW A-15 nFIQ A-11 ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. Index-3...
  • Page 190 8-2 TAPID A-10 TBIT 2-6 TCK 8-3 Test clock 8-3 register 2-9 Test Access Port 8-2 TESTEN A-14 Thumb instruction set 1-2 Typographical conventions xiii VINITHI A-11 Index-4 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A...

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