Table 4-3 Unalignment Fault Occurrence When Access Behavior Is Architecturally Unpredictable - ARM ARM1176JZF-S Technical Reference Manual

Table 4-3 Unalignment fault occurrence when access behavior is architecturally unpredictable

A U Addr[2:0]
0 0 -
0 0 bxxx
0 0 bxx0
0 0 bxx1
0 0 bxx0
0 0 bxx1
0 0 bxxx
0 0 bxxx
0 0 bx00
0 0 bxx1, bx1x
0 0 bxxx
0 0 b000
0 0 bxx1,
bx1x, b1xx
0 0 b000
0 0 bxx1,
bx1x,
b1xx
0 1 -
0 1 bxxx
ARM DDI 0301H
ID012310
Note
It is a consequence of these definitions that if X is word-aligned, Word[X]
consists of the same four bytes of actual memory in the same order in the LE and
BE-32 endianness models.
Align(X) This means X AND
to zero to make it word-aligned.
There is no difference between Addr and Align(Addr) on lines where Addr[1:0]
is set to b00. You can use this to simplify the control of when the least significant
bits are forced to zero.
For the Two-word and Multi-word access types, the Memory accessed column only specifies the
lowest word accessed. Subsequent words have addresses constructed by successively
incrementing the address of the lowest word by 4, and are constructed using the same endianness
model as the lowest word.
Access Architectural
types Behavior
- -
Byte, BSync Normal
Halfword Normal
Halfword Unpredictable
HWSync Normal
HWSync Unpredictable
Wload Normal
WStore Normal
WSync Normal
WSync Unpredictable
Multi-word Normal
Two-word Normal
Two-word Unpredictable
DWSync Normal
DWSync Unpredictable
- -
Byte, BSync Normal
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Non-Confidential, Unrestricted Access
Unaligned and Mixed-endian Data Access Support
. That is, X with its least significant two bits forced
0xFFFFFFFC
Memory accessed
-
Byte[Addr]
Halfword[Addr]
-
Halfword[Addr]
-
Word[Align32(Addr)]
Word[Align32(Addr)]
Word[Addr]
-
Word[Align32(Addr)]
Word[Addr]
-
Word[Addr]
-
-
Byte[Addr]
Note
Legacy, no alignment
Halfword[Align16(Addr)];
Operation unaffected by Addr[0]
Halfword[Align16(Addr)];
Operation unaffected by Addr[0]
Loaded data rotated by
8*Addr[1:0] bits
Operation unaffected by
Addr[1:0]
Word[Align32(Addr)]
Operation unaffected by
Addr[1:0]
Same as LDM2 or STM2
DWord[Align64(Addr)];
Operation unaffected by
Addr[2:0]
ARMv6 unaligned support
4-14