Qadd, Qdadd, Qsub, And Qdsub Instructions; Table 16-6 Qadd, Qdadd, Qsub, And Qdsub Instruction Cycle Timing Behavior - ARM ARM1176JZF-S Technical Reference Manual

16.4

QADD, QDADD, QSUB, and QDSUB instructions

ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for the QADD, QDADD, QSUB, and QDSUB
instructions.
These instructions perform saturating arithmetic. Their result is produced during the Sat stage,
consequently they have a result latency of two. The QDADD and QDSUB instructions must
double and saturate the register
of the pipeline, consequently this register is an Early Reg.
Table 16-6 lists the cycle timing behavior for QADD, QDADD, QSUB, and QDSUB
instructions.

Table 16-6 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior

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before the addition. This operation occurs in the Sh stage
<Rn>
Cycle
Instructions
s
QADD, QSUB 1
QDADD, QDSUB 1
Cycle Timings and Interlock Behavior
Early Reg Result latency
- 2
<Rn> 2
16-9