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Bits
Field name
[31:1]
-
[0]
C
ARM DDI 0301H
ID012310
Cache Dirty Status Register
The purpose of the Cache Dirty Status Register is to indicate when the Cache is dirty.
The Cache Dirty Status Register is:
•
in CP15 c7
•
a 32-bit read only register, banked for Secure and Non-secure worlds
•
accessible in privileged modes only.
Figure 3-43 shows the arrangement of bits in the Cache Dirty Status Register.
31
Table 3-74 lists how the bit value corresponds with the Cache Dirty Status Register function.
Function
UNP/SBZ.
The C bit indicates if the cache is dirty.
0 = indicates that no write has hit the cache since the last cache clean, clean and invalidate, or
invalidate all operation, or reset, successfully left the cache clean. This is the reset value.
1 = indicates that the cache might contain dirty data.
The Cache Dirty Status Register behaves in this way with regard to the Secure and Non-secure
cache:
•
clean, invalidate, and clean and invalidate operations of the whole cache in the Non-secure
world clear the Non-secure Cache Dirty Status Register
•
clear, invalidate, and clean and invalidate operations of the whole cache in the Secure
world clear both the Secure and Non-secure Cache Dirty Status Registers
•
if the core is in the Non-secure world or targets Non-secure data from the Secure world,
stores that write a dirty bit in the cache set both the Secure and the Non-secure Cache Dirty
Status Register
•
all stores that write a dirty bit in the cache set the Secure Cache Dirty Status Register.
All writes and User mode reads of the Cache Dirty Status Register cause an Undefined
exception.
To use the Cache Dirty Status Register read CP15 with:
•
Opcode_1 set to 0
•
CRn set to c7
•
CRm set to c10
•
Opcode_2 set to 6.
For example:
MRC p15, 0, <Rd>, c7, c10, 6
Copyright © 2004-2009 ARM Limited. All rights reserved.
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UNP/SBZ
Figure 3-43 Cache Dirty Status Register format
Table 3-74 Cache Dirty Status Register bit functions
; Read Cache Dirty Status Register.
System Control Coprocessor
1 0
C
3-78
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